1
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, Dept 18g, February 24, 2005: US20050040460-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


2
Xavier Baie
Dureseti Chidambarrao, Omer H Dokumaci, Bruce B Doris, Jack A Mandelman, Xavier Baie: Stress inducing spacers. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, June 17, 2004: US20040113217-A1

A substrate under tension and/or compression improves performance of devices fabricated therein. Tension and/or compression can be imposed on a substrate through selection of appropriate gate sidewall spacer material disposed above a device channel region wherein the spacers are formed adjacent both ...


3
Eb Eshun
Daniel C Edelstein, Anil K Chinthakindi, Timothy J Dalton, Ebenezer E Eshun, Jeffrey P Gambino, Sarah L Lane, Anthony K Stamper: Integrated Circuit Comb Capacitor. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, June 5, 2008: US20080130200-A1

The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention a ...


4
Eb Eshun
Ebenezer E Eshun, Ronald J Bolam, Douglas D Coolbaugh, Keith E Downes, Natalie B Feilchenfeld, Zhong Xiang He: Method and structure for creation of a metal insulator metal capacitor. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, November 15, 2007: US20070262416-A1

The invention is directed to an improved capacitor that reduces edge defects and prevents yield failures. A first embodiment of the invention comprises a protective layer adjacent an interface of a conductive layer with the insulator, while the second embodiment of the invention comprises a protecti ...


5
John T Phan, Michael Armand Roberge: Method and apparatus for DLL lock latency detection. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, April 1, 2004: US20040062137-A1 (2 worldwide citation)

Disclosed herein are a method and structure, in an integrated circuit having at least one delay locked loop circuit (DLL), for determining a Lock Latency value of a DLL output clock signal. The disclosed method includes temporarily disabling a first clock signal in response to the DLL doing at least ...


6
Ka Hing Fung, Atul C Ajmera, Victor Ku, Dominic J Schepis: Method for forming notch gate having self-aligned raised source/drain structure. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, September 19, 2002: US20020132431-A1 (2 worldwide citation)

An innovative MOSFET having a raised source drain (RSD) is constructed prior to implanting source-drain dopants. The RSD structure thus built has a distinct advantage in that the offset from the RSD to the MOSFET channel is fully adjustable to minimize the overlap capacitance in the device. The RSD ...


7
Lawrence Jacobowitz, John U Knickerbocker, Ronald P Luijten, Subhash L Shinde: Manufacturable optical connection assemblies. International Business Machines corporation, International Business Machines Corporation, Dept 18g, March 25, 2004: US20040057677-A1 (1 worldwide citation)

A set of interlocking modules supports and connects a die containing lasers, a set of precision molded lenses and a set of beam switching elements. Another embodiment of the invention is a structure for mounting a logic chip and an optical chip on a chip carrier, with the optical chip being mounted ...


8
William F Landers, Thomas M Shaw, Diana Llera Hurlburt, Scott W Crowder, Vincent J McGahay, Sandra G Malhotra, Charles R Davis, Ronald D Goldblatt, Brett H Engel: Multi-functional structure for enhanced chip manufacturibility & reliability for low k dielectrics semiconductors and a crackstop integrity screen and monitor. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, July 8, 2004: US20040129938-A1 (1 worldwide citation)

An on-chip redundant crack termination barrier structure, or crackstop, provides a barrier for preventing defects, cracks, delaminations, and moisture/oxidation contaminants from reaching active circuit regions. Conductive materials in the barrier structure design permits wiring the barriers out to ...


9
Lars W Liebmann, Carlos A Fonseca, Ioana Graur, Mark A Lavin: Alternating phase shift mask design with optimized phase shapes. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, May 15, 2003: US20030093766-A1 (1 worldwide citation)

A method is described for designing an alternating phase shifted mask (altPSM) by optimally selecting the width of phase shapes. The selection of optimal phase shape widths is achieved by providing a lithography metric that describes the relationship between phase shape width and the target image di ...


10
Mukta G Farooq, Mario Interrante, William Sablinski: Structure and method for lead free solder electronic package interconnections. International Business Machines Corporation, International Business Machines Corporation, Dept 18g, June 10, 2004: US20040108367-A1 (1 worldwide citation)

An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu ...



Click the thumbnails below to visualize the patent trend.