1
Ravi Rajwar, Maurice P Herlihy: Transactional memory execution utilizing virtual memory. Intel Corporation, David P McAbee, March 23, 2010: US07685365 (115 worldwide citation)

Embodiments of the invention relate to transactional memory execution utilizing virtual memory. A processor includes a local transactional cache and a resource manager. The resource manager responsive to a transactional memory transaction request from a requesting thread determines whether the local ...


2
Ravishankar Iyer, Ramesh Milekal, Donald Newell, Li Zhao: Priority aware selective cache allocation. Intel Corporation, David P McAbee, September 21, 2010: US07802057 (69 worldwide citation)

A method and apparatus for is herein described providing priority aware and consumption guided dynamic probabilistic allocation for a cache memory. Utilization of a sample size of a cache memory is measured for each priority level of a computer system. Allocation probabilities for each priority leve ...


3
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Fallk, Avi, Ilan Pardo, Eran Tamari, Ellezer Weissmann, Doron Shamia: PCI express enhancements and extensions. Intel Corporation, David P McAbee, May 24, 2011: US07949794 (32 worldwide citation)

A method and apparatus for enhancing /extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Mess ...


4
Quinn A Jacobson, Hong Wang, John Shen, Gautham N Chinya, Per Hammarlund, Xiang Zou, Bryant Bigbee, Shivnandan D Kaushik: Primitives to enhance thread-level speculation. Intel Corporation, David P McAbee, February 1, 2011: US07882339 (31 worldwide citation)

A processor may include an address monitor table and an atomic update table to support speculative threading. The processor may also include one or more registers to maintain state associated with execution of speculative threads. The processor may support one or more of the following primitives: an ...


5
Leaf Petersen, Bratin Saha, Ali Reza Adl tabatabai: Software assisted nested hardware transactions. Intel Corporation, David P McAbee, June 1, 2010: US07730286 (27 worldwide citation)

A method and apparatus for efficiently executing nested transactions is herein described. Hardware support for execution of transactions is provided. Additionally, through the use of logging previous values immediately before a current nested transaction in a local memory and storage of a stack of h ...


6
Natalie D Enright, Jamison D Collins, Perry Wang, Hong Wang, Xinmin Tran, John Shen, Gad Sheaffer, Per Hammarlund: Mechanism to exploit synchronization overhead to improve multithreaded performance. Intel Corporation, David P McAbee, September 8, 2009: US07587584 (18 worldwide citation)

Method, apparatus, and program means for a programmable event driven yield mechanism that may activate other threads. In one embodiment, an apparatus includes execution resources to execute a plurality of instructions and an event detector to detect a long latency event associated with a synchroniza ...


7
David Harriman, Jasmin Ajanovic: Communicating transaction types between agents in a computer system using packet headers including format and type fields. Intel Corporation, David P McAbee, August 25, 2009: US07581026 (16 worldwide citation)

A transmitting device and a receiving device are coupled via a high-speed serial interface within a computer system. The transmitting device transmits a packet that includes a format field to partially specify the packet header format and a type field to specify a transaction type. The format field ...


8
Perry H Wang, Hong Wang, John P Shen, Ashok N Seshadri, Anthony N Mah, William R Greene, Ravi K Chandran, Piyush Desai, Steve Shih wei Liao: User-programmable low-overhead multithreading. Intel Corporation, David P McAbee, December 8, 2009: US07631307 (16 worldwide citation)

A virtual multithreading hardware mechanism provides multi-threading on a single-threaded processor. Thread switches are triggered by user-defined triggers. Synchronous triggers may be defined in the form of special trigger instructions. Asynchronous triggers may be defined via special marking instr ...


9
Erik C Cota Robles, Stalinselvaraj Jeyasingh, Alain Kagi, Michael A Kozuch, Gilbert Neiger, Richard Uhlig: Invalidating translation lookaside buffer entries in a virtual machine (VM) system. Intel Corporation, David P McAbee, January 4, 2011: US07865670 (14 worldwide citation)

One embodiment of the present invention is a technique to invalidate entries in a translation lookaside buffer (TLB). A TLB in a processor has a plurality of TLB entries. Each TLB entry is associated with a virtual machine extension (VMX) tag word indicating if the associated TLB entry is invalidate ...


10
Jasmin Ajanovic, Mahesh Wagh, Prashant Sethi, Debendra Das Sharma, David Harriman, Mark Rosenbluth, Ajay Bhatt, Peter Barry, Scott Dion Rodgers, Anil Vasudevan, Sridhar Muthrasanallur, James Akiyama, Robert Blankenship, Ohad Falik, Abraham Mendelson, Ilan Pardo, Eran Tamari, Eliezer Weissmann, Doron Shamia: PCI express enhancements and extensions including transactions having prefetch parameters. Intel Corporation, David P McAbee, January 17, 2012: US08099523 (13 worldwide citation)

A method and apparatus for enhancing/extending a serial point-to-point interconnect architecture, such as Peripheral Component Interconnect Express (PCIe) is herein described. Temporal and locality caching hints and prefetching hints are provided to improve system wide caching and prefetching. Messa ...