1
L Brian Ji, Toshiaki Kirihata: Intra-unit block addressing system for memory. International Business Machines Corporation, Daryl K Neff Esq, March 14, 2000: US06038634 (88 worldwide citation)

A system is disclosed herein for stabilizing the current dissipation, voltage drop, and heating effects related to accessing blocks within first and second storage units of a double memory unit. The system includes a row selection unit located between the first and second storage units, which access ...


2
Harris C Jones, James G Ryan: Technique for extending the limits of photolithography. International Business Machines Corporation, McGinn & Gibb P C Daryl K Neff Esq, October 31, 2000: US06140217 (48 worldwide citation)

A method of forming a wiring pattern in a device comprises forming an array of grooves in a mask, forming first spacers adjacent vertical walls of the grooves, removing the mask, forming second spacers adjacent the first spacers, and filling areas between the first spacers and areas between the seco ...


3
Huilong Zhu, Oleg Gluschenkov, Chun Yung Sung: Method of fabricating a field effect transistor having improved junctions. International Business Machines Corporation, Daryl K Neff Esq, H Daniel Schnurmann, July 24, 2007: US07247547 (46 worldwide citation)

A method of forming a field effect transistor is provided which includes forming an amorphized semiconductor region having a first depth from a single-crystal semiconductor region and subsequently forming a first gate conductor above a channel portion of the amorphized semiconductor region. A first ...


4
Michael A Sorna: On-chip system and method for measuring jitter tolerance of a clock and data recovery circuit. International Business Machines Corporation, Daryl K Neff Esq, November 28, 2006: US07142623 (40 worldwide citation)

An integrated circuit is operable to measure tolerance to jitter in a data stream signal. A Clock And Data Recovery Circuit (“CDR”) thereon recovers a phase of a clock for sampling a data stream signal containing a repeatable known sequence of data values and then samples the data stream signal with ...


5
Ramachandra Divakaruni, Jeffrey P Gambino, Jack A Mandelman, Carl J Radens, William R Tonti: Shallow trench isolation method utilizing combination of spacer and fill. International Business Machines Corporation, Daryl K Neff Esq, McGinn & Gibb P C, November 21, 2000: US06150212 (35 worldwide citation)

A method for forming an isolation trench region in a semiconductor substrate includes providing the trench region in the semiconductor substrate, adding spacer material at least to sidewalls of the trench region, and etching the trench region at a bottom surface thereof to extend the trench region b ...


6
Philippe Coronel, Jean Canteloup: Method for real-time in-situ monitoring of a trench formation process. International Business Machines Corporation, Dale M Crockatt Esq, Daryl K Neff Esq, September 15, 1998: US05807761 (29 worldwide citation)

In the manufacturing of 16 Mbit DRAM chips, the deep trench formation process in a silicon wafer by plasma etching is a very critical step when the etching gas includes 0.sub.2. As a result, the monitoring of the trench formation process and thus the etch end point determination is quite difficult. ...


7
Jack A Mandelman, Gary B Bronner, Ramachandra Divakaruni: Method for providing dual work function doping and protective insulating cap. International Business Machines Corporation, Daryl K Neff Esq, McGinn & Gibb PLLC, August 28, 2001: US06281064 (28 worldwide citation)

A method for providing dual work function doping and borderless array diffusion contacts includes providing a semiconductor substrate, a gate insulator, a conductor on the gate insulator, an insulating cap on the conductor and insulating spacers on sidewalls of a portion of the conductor and the ins ...


8
Jack A Mandelman, Carl J Radens: MOSFET structure and process for low gate induced drain leakage (GILD). International Business Machines Corporation, Daryl K Neff Esq, McGinn & Gibb P C, August 1, 2000: US06097070 (27 worldwide citation)

A structure and method for forming a metal oxide semiconductor field effect transistor structure comprises, a substrate having a gate-channel region and source and drain regions adjacent the gate-channel region, a gate insulator over the substrate, a central gate conductor positioned above the gate- ...


9
Manfred Hauf, Max G Levy, Victor Ray Nastasi: Integrated circuit chip having isolation trenches composed of a dielectric layer with oxidation catalyst material. International Business Machines Corporation, Daryl K Neff Esq, Whitham Curtis Whitham & McGinn, February 24, 1998: US05721448 (22 worldwide citation)

An integrated circuit with FETs having an essentially uniform gate oxide thickness and FETs having gate oxide thickness enhanced along the sides. FETs with enhanced gate oxide have an ONO layer diffused with potassium in close proximity to the enhanced (thicker) oxide, and, as a result, have a sligh ...


10
Charles J Blasi, Gobinda Das, Franco Motika: Multi-layer ceramic substrate decoupling. International Business Machines Corporation, Daryl K Neff Esq, McGinn & Gibb P C, October 26, 1999: US05973928 (22 worldwide citation)

A multi-layer ceramic module comprises a multi-layer ceramic substrate having an upper side and a lower side, at least one semiconductor chip mounted on the upper side of the substrate, a plurality of module pins projecting from the lower side of the substrate and at least one decoupling capacitor m ...