1
Alfred J Reich, Kevin D Lucas, Michael E Kling, Warren D Grobman, Bernard J Roman: One dimensional lithographic proximity correction using DRC shape functions. Motorola, Daniel D HIll, May 4, 1999: US05900340 (196 worldwide citation)

Integrated circuit designs are continually shrinking in size. Lithographic processes are used to pattern these designs onto a semiconductor substrate. These processes typically require that the wavelength of exposure used during printing be significantly shorter than the smallest dimension of the el ...


2
James D Burnett: One transistor DRAM cell structure and method for forming. Freescale Semiconductor, James L Clingan Jr, Daniel D Hill, March 1, 2005: US06861689 (140 worldwide citation)

A single transistor DRAM cell is formed in a SOI substrate so that the DRAM cells are formed in bodies that are electrically isolated from each other. Each cell has doped regions that act as source and drain contacts. Between the drain contact and the body is a region, which aids in impact ionizatio ...


3
Douglas R Roberts, Eric Luckowski: Process for making a MIM capacitor. Motorola, Kim Marie Vo, Daniel D Hill, October 8, 2002: US06461914 (121 worldwide citation)

A process for forming a metal-insulator-metal (MIM) capacitor structure includes forming a recess in the dielectric layer (


4
Addi Burjorji Mistry, Vijay Sarihan, James H Kleffner, George F Carney: Method and apparatus for stress relief in solder bump formation on a semiconductor device. Motorola, Daniel D Hill, June 20, 2000: US06077726 (120 worldwide citation)

A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer ...


5
Howard E Levin: Method for fine gains adjustment in an ADSL communications system. Motorola, J Gustav Larson, Daniel D Hill, October 13, 1998: US05822374 (119 worldwide citation)

A communications system (30) includes a transceiver (42) for transmitting a plurality of bins. Individual bin BERs (bit-error-rates) are iteratively equalized. This is accomplished by applying a fine gains adjustment to the transmit power of the transceiver (42). Specifically, the BER of the bins is ...


6
Stephen T Flannagan, Ray Chang, Lawrence F Childs: Write control for a memory using a delay locked loop. Motorola, Daniel D Hill, August 8, 1995: US05440514 (101 worldwide citation)

A memory (20) includes a write control delay locked loop (52) for controlling a write cycle of the memory (20). The delay locked loop (52) includes an arbiter circuit (264), a voltage controlled delay (VCD) circuit (260), and a VCD control circuit (265). The arbiter circuit (264) compares a clock si ...


7
Michael Dean Snyder: Data processing system having a data prefetch mechanism and method therefor. Motorola, Daniel D Hill, Sandra L Godsey, June 6, 2000: US06073215 (100 worldwide citation)

A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not ...


8
Bernard J Pappert, Clark Shepard, Alfred Larry Crouch, Robert Ash: Method and apparatus for performing operative testing on an integrated circuit. Motorola, Sandra L Godsey, Daniel D Hill, July 27, 1999: US05929650 (97 worldwide citation)

A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built i ...


9
Lois E Yong, Peter R Harper, Tu Anh Tran, Jeffrey W Metz, George R Leal, Dieu Van Dinh: Semiconductor device having a bond pad and method therefor. Freescale Semiconductor, Daniel D Hill, James L Clingan Jr, January 18, 2005: US06844631 (87 worldwide citation)

A bond pad (10) has a probe region (14) and a wire bond region (12) that are substantially non-overlapping. In one embodiment, the bond pad (10) is connected to a final metal layer pad (16) and extends over an interconnect region (24). The bond pad (10) is formed from aluminum and the final metal la ...


10
Robert A Munroe, Stuart E Greer: Method for forming interconnect bumps on a semiconductor die. Motorola, Daniel D Hill, August 22, 2000: US06107180 (82 worldwide citation)

A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnec ...