Glen D Tindal: System and method for configuring a network device. Intelliden, Cooley Godward Kronish, July 17, 2007: US07246162 (34 worldwide citation)

A system and method for communicating with network devices without regard to the device type and/or manufacturer is described. In one embodiment, the present invention provides a global graphical user interface (GUI) for communicating with various network devices. The global GUI includes an intuitiv ...

Brian Foody: Pre-treatment of bales of feedstock. Iogen Energy Corporation, Cooley Godward Kronish, April 3, 2007: US07198925 (34 worldwide citation)

The present invention is directed to a method of pre-treating a lignocellulosic feedstock. The lignocellulosic feedstock comprises cereal straw, stover, or grass. One or more than one bale of lignocellulosic feedstock is conveyed into a pre-treatment reactor. Steam and acid are added to the bales an ...

Brian M Kelleher: Multi-chip graphics processing unit apparatus, system, and method. NVIDIA Corporation, Cooley Godward Kronish, October 6, 2009: US07598958 (33 worldwide citation)

A multi-chip graphics system includes a master chip and a slave chip coupled by an interlink. The slave chip performs a graphics processing operation in parallel with the master chip, improving the performance of the master chip. In one embodiment, an individual graphics processing unit (GPU) chip i ...

William P Tsu, Luc R Bisson, Oren Rubinstein, Wei Je Huang, Michael B Diamond: Apparatus, system, and method for bus link width optimization of a graphics system. NVIDIA Corporation, Cooley Godward Kronish, September 16, 2008: US07426597 (33 worldwide citation)

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.

Philip Richard Buzby: Methods and compositions for improving fidelity in a nucleic acid synthesis reaction. Helicos Biosciences Corporation, Cooley Godward Kronish, Konstantin M Linnik, Thomas C Meyers, January 27, 2009: US07482120 (32 worldwide citation)

The invention provides methods and compositions for improving the fidelity of a sequencing-by-synthesis reaction by using a nucleotide derivative that forms a hydrogen bond with a complementary nucleotide on a template, but fails to form a phosphodiester bond with the 3′ hydroxyl group of a primer u ...

Bryon S Nordquist, Stephen D Lew: Apparatus, system, and method for coalescing parallel memory requests. Nvidia Corporation, Cooley Godward Kronish, February 17, 2009: US07492368 (32 worldwide citation)

A multiprocessor system executes parallel threads. A controller receives memory requests from the parallel threads and coalesces the memory requests to improve memory transfer efficiency.

Jun Young Yang, You Ock Joo, You Pil Jung: Semiconductor device package and manufacturing method. Advanced Semiconductor Engineering, Cooley Godward Kronish, February 2, 2010: US07656047 (32 worldwide citation)

A semiconductor device package includes a semiconductor device mounted and electrically coupled to a substrate, a package body encapsulating the semiconductor device against a portion of an upper surface of the substrate; and an electromagnetic interference shielding layer formed over the package bo ...

Graham Vesey: Process for preparing control samples of particles such as microorganisms and cells. BTF, Cooley Godward Kronish, March 6, 2007: US07186502 (32 worldwide citation)

Processes for preparing controlled samples of particles, including microorganisms and cells are described. A sample of particles is provided and separated into a predetermined number of desired particles by particle separation means. The predetermined number of particles is dispensed into a receptac ...

Ziyad S Hakura, Michael Brian Cox, Brian K Langendorf, Brad W Simeral: Apparatus, system, and method for Z-culling. Nvidia Corporation, Cooley Godward Kronish, November 11, 2008: US07450120 (31 worldwide citation)

A processor generates Z-cull information for tiles and groups of tiles. In one embodiment the processor includes an on-chip cache to coalesce Z information for tiles to identify occluded tiles. In a coprocessor embodiment, the processor provides Z-culling information to a graphics processor.

John S Montrym, David B Glasco, Steven E Molnar: Apparatus, system, and method for using page table entries in a graphics system to provide storage format information for address translation. NVIDIA Corporation, Cooley Godward Kronish, June 9, 2009: US07545382 (31 worldwide citation)

A graphics system utilizes page table entries to provide information on the storage format used to store graphics data. The page table entries, in turn, may be used for address translation. Exemplary kinds of storage format information include compression mode, a packing mode for storing Z data in t ...