1
Keith E Diefendorff, William C Anderson: Method for executing graphics Z-compare and pixel merge instructions in a data processor. Motorola, Charlotte B Whitaker, December 7, 1993: US05268995 (209 worldwide citation)

A method for performing graphics Z-compare and pixel merge operations, for use in a Z-buffering system to remove hidden surfaces when displaying a three-dimensional image, is provided. The data processing system includes a main memory for storing data and instructions, and a graphics execution unit ...


2
Nigel J Allison, Rand L Gray, Jay A Hartvigsen: No-chip debug peripheral which uses externally provided instructions to control a core processing unit. Motorola, Charlotte B Whitaker, October 1, 1991: US05053949 (112 worldwide citation)

A data processing system having a debug peripheral is provided. The debug peripheral is coupled to a central processing unit and memory via an internal communications bus. The debug peripheral is a single-word dual port memory with parallel read-write write access on one side, and synchronous, full- ...


3
Michael C Shebanow, Mitchell Alsup: Data processor for performing simultaneous instruction retirement and backtracking. Motorola, Charlotte B Whitaker, October 11, 1994: US05355457 (106 worldwide citation)

A data processing system is provided which has more general purpose physical registers than architectural (logical) registers. The data processing system uses a register inventory system to monitor the allocation state changes of each of the physical registers in a register file. As a sequencer issu ...


4
Robin W Edenfield, William B Ledbetter Jr, Russell A Reininger: System for transferring selected data words between main memory and cache with multiple data words and multiple dirty bits for each address. Motorola, Charlotte B Whitaker, October 13, 1992: US05155824 (103 worldwide citation)

A data cache capable of operation in a write-back (copyback) mode. The data cache design provides a mechanism for making the data cache coherent with memory, without writing the entire cache entry to memory, thereby reducing bus utilization. Each data cache entry is comprised of three items: data, a ...


5
Terry L Biggs, Antonio A Lagana: Data processor having a cache memory capable of being used as a linear ram bank. Motorola, Charlotte B Whitaker, April 25, 1995: US05410669 (68 worldwide citation)

A data processing system (10) having a dual purpose memory (14) comprising multiple cache sets. Each cache set can be individually configured as either a cache set or as a static random access memory (SRAM) bank. Based upon the configuration of the set, the tag store array (58) is used for storage o ...


6
Mark W McDermott, Ernest A Carter: MOS output buffer with reduced supply line disturbance. Motorola, Charlotte B Whitaker, September 25, 1990: US04959561 (61 worldwide citation)

An output buffer with reduced supply line disturbance is provided for use in high performance microprocessor circuits. The output buffer uses a resistor and transistor as a sensing circuit, in parallel with an output driver transistor, thereby providing a negative feedback path into the control circ ...


7
James R Lundberg, Charles E Nuckolls: Method and apparatus for performing frequency detection. Motorola, Charlotte B Whitaker, April 23, 1996: US05511100 (59 worldwide citation)

A method and apparatus for performing frequency detection in an all digital phase lock loop (10). Frequency detection is accomplished using a frequency detector (11), coupled to an digitally controlled oscillator (DCO 16). The frequency detector (11) forces phase alignment of a reference clock signa ...


8
Mitchell Alsup, Carl S Dobbs, Yung Wu, Claude Moughanni, Elie I Haddad: Digital phase lock clock generator without local oscillator. Motorola, Charlotte B Whitaker, December 22, 1992: US05173617 (55 worldwide citation)

A digital phase lock loop that does not depend on a voltage controlled oscillator (VCO) for phase locking. A phase detector (PD), terminated with a latch, controls an up/down counter that programs an increase/decrease of delay on the delay line. The tapped output of the delay line goes through a two ...


9
James B Gullette, William C Moyer, Michael J Garcia: Method and apparatus for performing a snoop-retry protocol in a data processing system. Motorola, Charlotte B Whitaker, April 9, 1996: US05506971 (44 worldwide citation)

A data processing system (10) and method for performing a snoop-retry protocol using an arbiter (14). Multiple bus masters (12, 16, 17) are coupled to multiple shared buses (20, 22, 24, 26). Each bus master (12, 16, 17) may initiate a bus transaction ("initiating master"), or snoop the bus transacti ...


10
William C Moyer, James B Gullette, Michael J Garcia: Method and apparatus for performing bus arbitration in a data processing system. Motorola, Charlotte B Whitaker, May 16, 1995: US05416910 (43 worldwide citation)

A data processing system (10) and method for performing bus arbitration protocol using an arbiter (14). The data processing system (10) has multiple bus masters (12, 16) each of which is coupled to multiple shared buses (20, 22, 24, 28). The arbiter (14) detects a bus request from a requesting bus m ...