1
Michael Norman Day, Charles Ray Johns, James Allan Kahle, Peichum Peter Liu, Thuong Quang Truong: Method to Provide Atomic Update Primitives in an Asymmetric Heterogeneous Multiprocessor Environment. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, January 18, 2007: US20070016733-A1

The present invention provides for atomic update primitives in an asymmetric single-chip heterogeneous multiprocessor computer system having a shared memory with DMA transfers. At least one lock line command is generated from a set comprising a get lock line command with reservation, a put lock line ...


2
Kenneth O Brinson, Sanjay Gupta, Binh T Hoang, James M Stafford: Apparatus and method for testing sub-systems of a system-on-a-chip using a configurable external system-on-a-chip. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, January 18, 2007: US20070016880-A1

An apparatus and method are provided in which a previously verified SoC is coupled to a SoC under test via a communication bus or other type of communication interface. The previously verified SoC is provided with the same test stimuli as the SoC under test and thus, generates expected test results ...


3
David William Boerstler, Eskinder Hailu, Harm Peter Hofstee, John Samuel Liberty: Oscillator array with row and column control. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 5, 2006: US20060220753-A1

A circuit topology which can be used to create an array of individually tuned oscillators operating at different frequencies determined by common control inputs and an easily managed variation in design dimensions of several components is provided. An array of oscillators are provided arranged in co ...


4
Jonathan James DeMent, Kurt Alan Feiste, David Scott Ray, David Shippy, Albert James Van Norstrand: System and method for handling multi-cycle non-pipelined instruction sequencing. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 5, 2006: US20060224864-A1

A system and method for handling multi-cycle non-pipelined instruction sequencing. With the system and method, when a non-pipelined instruction is detected at an issue point, the issue logic initiates a stall that is for a minimum number of cycles that the fastest non-pipelined instruction could com ...


5
Brian King Flachs, Brad William Michael: Combination of forwarding/bypass network with history file. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 5, 2006: US20060224869-A1

An apparatus, a method, and a processor are provided for recovering the correct state of processor instructions in a processor. This apparatus contains a pipeline of latches, a register file, and a replay loop. The replay loop repairs incorrect results and inserts the repaired results back into the ...


6
Anand Haridass, Dierk Kaller, Erich Klink, Gisbert Gerhard Thomke: System and method for increasing wiring channels/density under dense via fields. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 5, 2006: US20060219427-A1

A system and method for increasing the wiring channels/density under dense via fields of a circuit board are provided. With the system and method, the power/ground lines for the circuit board are designed to be provided in an orthogonal or diagonal pattern. The land grid array (LGA)/ball grid array ...


7
Dharmesh N Bhakta, Trung Q Ly, Juan Francisco Obas, Lakshmi N Potluri: System and method for synchronizing distributed data streams for automating real-time navigation through presentation slides. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 19, 2006: US20060235927-A1

A system and method for synchronizing distributed data streams for automating real-time navigation through presentation slides in an electronic conference are provided. With the system and method, a participant in an electronic conference is permitted to navigate back and forth through a series of p ...


8
Guruprasad Baskaran, Kulvir Singh Bhogal, Kanmani Nachimuthu, Lakshmi Potluri: System and method for enhanced layer of security to protect a file system from malicious programs. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, October 19, 2006: US20060236100-A1

A system and method for providing an enhanced layer of security to protect the file system from malicious programs are provided. An additional layer of security for protecting data and to minimize successful attacks by malicious programs is provided. This additional layer uses the feature of code si ...


9
Paul Allen Ganfield, Kent Harold Haselhorst, Charles Ray Johns, Peichun Peter Liu: Method to handle rambus write mask. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, November 23, 2006: US20060265546-A1

A method, an apparatus, and a computer program product are provided for the handling of write mask operations in an XDR DRAM memory system. This invention eliminates the need for a two-port array because the mask generation is done as the data is received. Less logic is needed for the mask calculati ...


10
William Todd Boyd, John Lewis Hufferd, Agustin Mena, Renato John Recio, Madeline Vega: System and method for out of user space block mode I/O directly between an application instance and an I/O adapter. Ibm, c o WALDER INTELLECTUAL PROPERTY LAW PC, November 23, 2006: US20060265561-A1

The present invention provides a system, method, and computer program product that enables application instances to pass block mode storage requests directly to a physical I/O adapter without run-time involvement from the local operating system or hypervisor. Specifically, a mechanism for providing ...