1
Puneet Gupta, Fook Luen Heng, Mark A Lavin: Method of IC fabrication, IC mask fabrication and program product therefor. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Brian P Verminski Esq, April 1, 2008: US07353492 (170 worldwide citation)

A method of forming integrated circuit (IC) chip shapes and a method and computer program product for converting an IC design to a mask, e.g., for standard cell design. Individual book/macro physical designs (layouts) are proximity corrected before unnesting and an outer proximity range is determine ...


2
Syed M Alam, Ibrahim M Elfadel, Kathryn W Guarini, Meikei Ieong, Prabhakar N Kudva, David S Kung, Mark A Lavin, Arifur Rahman: Three dimensional integrated circuit and method of design. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, May 25, 2010: US07723207 (85 worldwide citation)

A three dimensional (3D) integrated circuit (IC), 3D IC chip and method of fabricating a 3D IC chip. The chip includes multiple layers of circuits, e.g., silicon insulator (SOI) CMOS IC layers, each including circuit elements. The layers may be formed in parallel and one layer attached to another to ...


3
Yael Ravin, James J Sharpe, Edith H Stern: Knowledge management system automatically allocating expert resources. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Brian P Verminski Esq, January 4, 2011: US07865457 (34 worldwide citation)

A knowledge management system allocating expert resources, method of allocating expert resources and program product therefor. Information requests are provided over networked devices, e.g., over voice and data networks. Data on experts may be stored in an expert database and data on requesters stor ...


4
John M Cohn, James A Culp, Ulrich A Finkler, Fook Luen Heng, Mark A Lavin, Jin Fuw Lee, Lars W Liebmann, Gregory A Northrop, Nakgeuon Seong, Rama N Singh, Leon Stok, Pieter J Woltgens: Physical design system and method. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Brian P Verminski Esq, May 19, 2009: US07536664 (28 worldwide citation)

A design system for designing complex integrated circuits (ICs), a method of IC design and program product therefor. A layout unit receives a circuit description representing portions in a grid and glyph format. A checking unit checks grid and glyph portions of the design. An elaboration unit genera ...


5
Howard Hao Chen, Louis Lu Chen Hsu: Device and method for fabricating double-sided SOI wafer scale package with optical through via connections. International Business Machines Corporation, Keusey Tutunjian & Bitetto P C, Brian P Verminski Esq, February 10, 2009: US07489025 (27 worldwide citation)

A semiconductor package includes an SOI wafer having a first side including an integrated circuit system, and a second side, opposite the first side, forming at least one cavity. At least one chip or component is placed in the cavity. An optical through via is formed through a buried oxide which opt ...


6
Dirk Husemann, Michael Moser: Method and apparatus for providing a more powerful user-interface to device with a limited user-interface. International Business Machines Corporation, Brian P Verminski Esq, August 18, 2009: US07577910 (25 worldwide citation)

A method and apparatus for controlling a computer device with a limited user-interface via a remote computer device having a more powerful user interface. Both computer devices are interconnected via a wireless communication channel and both computer devices support a common communications protocol. ...


7
Pradip Bose, Chen Yong Cher, Hubertus Franke, Hendrik Hamann, Eren Kursun, Alan J Weger: Method of virtualization and OS-level thermal management and multithreaded processor with virtualization and OS-level thermal management. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, February 8, 2011: US07886172 (25 worldwide citation)

A program product and method of managing task execution on an integrated circuit chip such as a chip-level multiprocessor (CMP) with Simultaneous MultiThreading (SMT). Multiple chip operating units or cores have chip sensors (temperature sensors or counters) for monitoring temperature in units. Task ...


8
Phillip J Restle: Resonant tree driven clock distribution grid. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Brian P Verminski Esq, August 4, 2009: US07571410 (16 worldwide citation)

An integrated circuit (IC), IC assembly and circuit for distributing a clock signal in an integrated circuit includes a capacitive clock distribution circuit having at least one conductor therein. At least one inductor is formed in a metal layer of the integrated circuit and is coupled to the clock ...


9
Robert L Franch, William V Huott, Norman K James, Phillip J Restle, Timothy M Skergan: Built in self test circuit for measuring total timing uncertainty in a digital data path. International Business Machines Corporation, Law Office of Charles W Peterson Jr, Louis J Percello Esq, Brian P Verminski Esq, July 15, 2008: US07400555 (12 worldwide citation)

A circuit for measuring timing uncertainty in a clocked digital path and in particular, the number of logic stages completed in any clock cycle. A local clock buffer receives a global clock and provides a complementary pair of local clocks. A first local (launch) clock is an input to a delay line, e ...


10
Christian Ivo Menolfi, Thomas Helmut Toifl: Phase locked loop apparatus with adjustable phase shift. International Business Machines Corporation, Keusey Tutunjian & Bitetto P C, Brian P Verminski Esq, February 17, 2009: US07492850 (11 worldwide citation)

The phase locked loop (PLL) with adjustable phase shift is described. The PLL includes a voltage controlled oscillator which is capable of generating multiple phase shifted output signals, and multiple phase detectors capable of determining the phase differences between the output signals and a refe ...



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