1
Kelly S Carpenter, Gerard M Dearing, Jeffrey M Nick, Jimmy P Strickland, Michael D Swanson, Wendell W Wilkinson: Coherence controls for store-multiple shared data coordinated by cache directory entries in a shared electronic storage. International Business Machines Corporation, Bernard M Goldman, August 6, 1996: US05544345 (639 worldwide citation)

A high-speed cache is shared by a plurality of independently-operating data systems in a multi-system data sharing complex. Each data system has access both to the high-speed cache and to lower-speed, upper-level storage for obtaining and storing data. Management logic in the shared high-speed cache ...


2
William F Beausoleil, Tak Kwong Ng, Harold R Palmer: Multiprocessor for hardware emulation. International Business Machines Corporation, Bernard M Goldman, August 27, 1996: US05551013 (393 worldwide citation)

A software-driven multiprocessor emulation system comprising a plurality of emulation processors connected in parallel in a module. One or more modules of processors comprise an emulation system. An execution unit in each processor includes a table-lookup unit for emulating any type of logic gate fu ...


3
Casper Anthony Scalzi, Eric Mark Schwarz, William John Starke, James Robert Urquhart, Douglas Wayne Westcott: Preprocessing of stored target routines for emulating incompatible instructions on a target processor. International Business Machines Corporation, Marc A Ehrlich, Bernard M Goldman, December 28, 1999: US06009261 (338 worldwide citation)

Provides a program translation and execution method which stores target routines (for execution by a target processor) corresponding to incompatible instructions, interruptions and authorizations of an incompatible program written for execution on another computer system built to a computer architec ...


4
George H Bean, Terry L Borden, Mark S Farrell, Peter H Gum, Roger E Hough, Francis E Johnson, Donald W McCauley, Mark E Rakhmilevich, John C Rathjen, Casper A Scalzi, John F Scanlon, Leslie W Wyman: Logical resource partitioning of a data processing system. International Business Machines Corporation, Bernard M Goldman, June 27, 1989: US04843541 (299 worldwide citation)

The embodiment discloses a method and means for partitioning the resources in a data processing system into a plurality of logical partitions. Host control code may be embodied in programming, microcode, or by special hardware to enable highly efficient operation of a plurality of preferred guest pr ...


5
Richard R Guyette, Eddie T Hall, Allan S Meritt, Stephen R Newson, Casper A Scalzi, Glenn W Sears Jr: Partitioned multiprocessor programming system. International Business Machines Corporation, Bernard M Goldman, January 14, 1986: US04564903 (198 worldwide citation)

The disclosure provides a unique multiprocessing (MP) method for executing on plural CPUs of the MP a uniprocessor system (UPS) program not written to run on a MP system. Separate copies of the UPS are provided in the shared main storage (MS) of the MP. A hypervisor type of control program (called a ...


6
Casper A Scalzi, William J Starke: Method of using a target processor to execute programs of a source architecture that uses multiple address spaces. International Business Machines Corporation, Bernard M Goldman, September 24, 1996: US05560013 (186 worldwide citation)

A method of utilizing large virtual addressing in a target computer to implement an instruction set translator (1ST) for dynamically translating the machine language instructions of an alien source computer into a set of functionally equivalent target computer machine language instructions, providin ...


7
Patrick M Gannon, Peter H Gum, Roger E Hough, Robert E Murray: Apparatus and method for TLB purge reduction in a multi-level machine system. International Business Machines Corporation, Bernard M Goldman, May 31, 1994: US05317705 (184 worldwide citation)

A system for reducing purging of a translation lookaside buffer (TLB) to reduce operating system overhead in a system running multiple levels of virtual machines. A system typically must purge TLB entries whenever an underlying page table entry is invalidated due to paging activity on the host machi ...


8
Arthur L Levin, Don W Rain, David J Thomas: Internal performance monitoring by event sampling. International Business Machines Corporation, Bernard M Goldman, April 11, 1989: US04821178 (178 worldwide citation)

The disclosure provides event-controlled operations for an internal hardware/softward monitor for a processor in a data processing system. It embeds and distributes in each processor at least one instrumentation table unit (ITU) and event detection circuitry to detect events and conditions for colle ...


9
Frank W Brice Jr, Joseph C Elliott, Kenneth J Fredericks, Robert E Galbraith, Marten J Halma, Roger E Hough, Suzanne M John, Paul A Malinowski, Allan S Meritt, Kenneth J Oakes, John C Rathjen Jr, Martin W Sachs, David E Stucki, Leslie W Wyman: Method and means for sharing I/O resources by a plurality of operating systems. International Business Machines Corporation, Bernard M Goldman, May 9, 1995: US05414851 (150 worldwide citation)

Provides a method for increasing the connectivity of I/O resources to a multiplicity of operating systems (OSs) running in different resource partitions of a computer electronic complex (CEC) to obtain sharing of the I/O resources among the OSs of the CEC, including channels, subchannels (devices), ...


10
John H Eilert, Arthur L Levin, Thomas Julian: Internally distributed monitoring system. International Business Machines Corporation, Bernard M Goldman, May 20, 1986: US04590550 (148 worldwide citation)

The disclosure provides an embedded hardware/software monitor for a data processing system. It embeds and distributes a plurality of instrumentation table units (ITUs) within various hardware entities in the system to collect sampled hardware signals local in the hardware entity in which the respect ...