1
Khue Duong: Tile-based modular routing resources for high density programmable logic device. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, March 9, 1999: US05880598 (232 worldwide citation)

Signal routing resource tiles that can be manipulated as circuit "cells" in that they can be readily characterized and implemented on a programmable logic device, e.g., a field programmable gate array (FPGA). In one embodiment, vertical placement and horizontal placement routing resource tiles are p ...


2
Stephen M Trimberger: DRAM memory cell for programmable logic devices. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, December 8, 1998: US05847577 (107 worldwide citation)

A plurality of DRAM cells are used to store the state of the programmable points in a programmable logical device (e.g., a field programmable gate array or FPGA). An individual DRAM cell is used in conjunction with each programmable interconnect point (PIP) within the FPGA to hold a logical state in ...


3
Stephen M Trimberger: Programmable logic array with improved interconnect structure. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, December 8, 1998: US05847579 (75 worldwide citation)

A programmable logic array improves connectivity and more efficiently routes signals between logic blocks by allowing programmable connections between each logic block and the horizontal interconnect lines above and below the logic block. Thus, more efficient signal transfer is achieved, particularl ...


4
Robert O Conn: Method for characterizing interconnect timing characteristics using reference ring oscillator circuit. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, August 4, 1998: US05790479 (46 worldwide citation)

A reference ring oscillator circuit (RROC) is used to determine timing characteristics of a test interconnect structure in an integrated circuit. The RROC includes an odd number of inverters coupled together in a ring manner and has defined test segments at which a test interconnect can be loaded. R ...


5
Sheau Suey Li, Randy T Ong, Samuel Broydo, Khue Duong: ESD protection circuit. Xilinx, Anthony C Wagner Murabito & Hao Murabito Esq, Edel M Young Xilinx, November 18, 1997: US05689133 (32 worldwide citation)

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures a ...


6
Neil G Jacobson, Anthony S Maraldo: Processing unit for generating signals for communication with a test access port. Xilinix, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, December 2, 1997: US05694399 (24 worldwide citation)

A system for interfacing with a test access communication port. Specifically, the present invention has application to the IEEE 1149.1 Test Access Port ("JTAG") standard. The novel system includes a hardware unit having a memory unit and a special processor unit (SPU) that interfaces between the tes ...


7
Philip M Freidin, Stephen M Trimberger, John E Mahoney, Charles R Erickson: Configurable parallel and bit serial load apparatus. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, December 1, 1998: US05844829 (13 worldwide citation)

An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each dat ...


8
Philip M Freidin, Stephen M Trimberger, John E Mahoney, Charles R Erickson: Configurable parallel and bit serial load apparatus. Xilinx, Anthony C Wagner Murabito & Hao Murabito, Jeanette S Harms, October 5, 1999: US05961576 (8 worldwide citation)

An apparatus for loading configuration information into a programmable integrated circuit (e.g., an FPGA) configurable to perform parallel loading or bit serial loading within the same architecture. The configuration information is presented to the FPGA in data frames of N serial bits each. Each dat ...