1
Alan S Fisher, Samuel Jerrold Kaplan: Method and system for processing and transmitting electronic auction information. Onsale, Adam H Tachner, Crosby Heafey Roach & May, June 5, 2001: US06243691 (452 worldwide citation)

A system and method for conducting a multi-person, interactive auction, in a variety of formats, without using a human auctioneer to conduct the auction. The system is preferably implemented in software. The system allows a group of bidders to interactively place bids over a computer or communicatio ...


2
Stephen M Trimberger: PLD having a window pane architecture with segmented and staggered interconnect wiring between logic block arrays. Xilinx, Adam H Tachner, Jeanette S Harms, July 4, 2000: US06084429 (253 worldwide citation)

A window pane architecture for FPGAs utilizes spaced subarrays having routing channels therebetween. In one embodiment, at least one routing channel includes segmented and staggered routing wires to minimize current loading and capacitive time delay. Connections between the configurable logic blocks ...


3
Danesh Tavana, Wilson K Yee, Stephen M Trimberger: Integrated circuit with field programmable and application specific logic areas. Xilinx, Edel M Young, Adam H Tachner, Lois D Cartier, October 20, 1998: US05825202 (235 worldwide citation)

A heterogeneous integrated circuit device comprising a field programmable gate array (FPGA) programmably connected to a mask-defined application specific logic area (ASLA) on an integrated circuit thus providing a flexible low cost alternative to a homogeneous device of one type or the other. By int ...


4
Stan S Hahn: Universally interchangeable and modular power supply with integrated battery charger. Asian Micro Sources, Adam H Tachner, Nathan P Crosby Heafey Roach & May Koenig, July 15, 1997: US05648712 (186 worldwide citation)

An integrated power supply and battery charger with interchangeable and collapsible plug capacity and interchangeable power input modules includes a casing, an electrical plug detachably mounted in the casing and including collapsible prongs, allowing the user to accommodate myriad combinations of p ...


5
Brad Taylor: Pld connector for module having configuration of either first PLD or second PLD and reconfigurable bus for communication of two different bus protocols. Giga Operations Corporation, Adam H Tachner, David J Larwood, Crosby Heafey Roach & May, July 9, 1996: US05535342 (169 worldwide citation)

A module for supporting and connecting programmable logic devices through a common interface. A card in the PC Card format is provided with bus interface support for interconnection to other such modules. The module supports one or more programmable logic devices, each of which is connectable to fou ...


6
Stephen M Trimberger: Reprogrammable instruction set accelerator using a plurality of programmable execution units and an instruction page table. Mark A Haynes, Adam H Tachner, Jeanette S Harms, May 5, 1998: US05748979 (144 worldwide citation)

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined, fixed set of instructions, combined with one or more programmable execution units coupled to the internal buses for execution of a programmed instruction providing an on chip ...


7
Stephen M Trimberger, Jonathan S Rose: State saving and restoration in reprogrammable FPGAs. Xilinx, Edel M Young, Adam H Tachner, December 1, 1998: US05844422 (140 worldwide citation)

Structures for saving states of memory cells in an FPGA while the FPGA is being configured are shown. Structures for saving flip flop states, lookup table configurations, and block RAM states are specifically described. Structures are described having (1) a SAVE STATE bit for saving the state of eac ...


8
Sundararajarao Mohan, Stephen M Trimberger: Method for configuring FPGA memory planes for virtual hardware computation. Xilinx, Adam H Tachner, Jeanette S Harms, April 4, 2000: US06047115 (130 worldwide citation)

A dynamically reconfigurable FPGA includes an array of tiles on a logic plane and a plurality of memory planes. Each tile has associated storage elements on each memory plane, called local memory. This local memory allows large amounts of data to pass from one FPGA configuration (memory plane) to an ...


9
Stephen M Trimberger: Reprogrammable instruction set accelerator. Mark A Haynes, Adam H Tachner, Jeanette S Harms, April 7, 1998: US05737631 (122 worldwide citation)

A microprocessor comprises a defined execution unit coupled to internal buses of the processor for execution of a predefined set of instructions, combined with a programmable execution unit coupled to the internal buses for execution of a programmed instruction providing an on chip reprogrammable in ...


10
Gary R Lawman, Robert W Wells: Concurrent electronic circuit design and implementation. Xilinx, Edel M Crosby Heafey Roach & May Young, Adam H Tachner, September 30, 1997: US05673198 (115 worldwide citation)

A system for providing real time design feedback to a user of a data processing system for designing an electronic circuit includes a display system, a graphical, textual or mixed user input process which displays user input on the display system for designing an electronic circuit, and an implement ...