1
Balmukund Sharma, Mossaddeq Mahmood, Arnold Ginetti: Apparatus and method for synthesizing integrated circuits using parameterized HDL modules. VLSI Technology, William S Galliani, Flehr Hohbach Test Albritton & Herbert, November 24, 1998: US05841663 (282 worldwide citation)

A method and apparatus for designing circuits uses parameterized Hardware Description Language (HDL) modules stored in a library. A datapath synthesizer accesses the library and assigns values to parameters to form specific implementations of the parameterized HDL modules. The specific implementatio ...


2
Joseph A Thomsen, David R Evoy: Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus. VLSI Technology, Harry M Weiss, April 4, 1995: US05404460 (223 worldwide citation)

An electronic system has multiple identical Input/Output (I/O) devices which are all connected in daisy-chain fashion on a serial bus. At power-up or reset, the I/O device at the end of the chain configures itself as Device 0, and outputs data to the next device which configures it as Device 1. Devi ...


3
Young I Kwon: Exposed die-attach heatsink package. VLSI Technology, Hickman & King, April 6, 1993: US05200809 (220 worldwide citation)

A technique for packaging an integrated-circuit die in a conventional molded-plastic package exposes the lead frame to which the integrated-circuit die is attached so that heat-conducting columns can be directly attached to the leadframe through vias formed in the molded plastic package. The vias ex ...


4
Richard J Takahashi: Dual purpose security architecture with protected internal operating system. VLSI Technology, Douglas L Weller, March 25, 1997: US05615263 (215 worldwide citation)

A secure mode within a dual mode processor is implemented. In a general/external mode, the dual mode processor executes instructions provided from an external source. The instructions are supplied to the processor via input/output to the processor. Upon receiving a special software or hardware inter ...


5
Louis Liang, Sang S Lee, Young I Kwon: Integrated circuit package having an interposer. VLSI Technology, Hickman & Beyer, July 26, 1994: US05332864 (214 worldwide citation)

An integrated circuit package characterized by an interposer including a thin, flexible, planar insulator having a plurality of substantially radial traces provided on one side thereof. The other side of the insulator is attached to the die attach pad of a lead frame, and an integrated circuit die i ...


6
Tsing Chow Wang, Louis H Liang: Semi-conductor device interconnect package assembly for improved package performance. VLSI Technology, Majestic Parsons Siebert & Hsue, May 9, 1995: US05414299 (194 worldwide citation)

A semiconductor device interconnect package assembly for TAB packages is disclosed having a central portion of material which is utilized as part of the package structure to provide scratch protection to the active surface of a semiconductor die and to the inner lead bonding areas. The central porti ...


7
Kamran Manteghi: Electrically enhanced power quad flat pack arrangement. VLSI Technology, Patrick T King, July 8, 1997: US05646831 (192 worldwide citation)

A quad flat pack arrangement which provides for an electrically enhanced integrated-circuit package structure is disclosed. An integrated-circuit die is centrally attached to the top surface of a thermally-conductive, and electrically conductive or insulated substrate. A lead frame having a pluralit ...


8
Calvin Todd Gabriel, Jacob Haskell, Satyendra Sethi: Sacrificial multilayer anti-reflective coating for mos gate formation. VLSI Technology, Woodard Emhardt Naughton Moriarty & McNett, October 2, 2001: US06297170 (174 worldwide citation)

The present invention relates to semiconductor devices in general, and more particularly to semiconductor devices having anti-reflective coatings to aid in the patterning of a reflective layer thereon to form, for example, a gate electrode. The invention also relates to methods for making a semicond ...


9
Paul S Levy, Steve Cornelius: Secure data communication over a memory-mapped serial communications interface utilizing a distributed firewall. VLSI Technology, Wood Herron & Evans L, April 3, 2001: US06212633 (172 worldwide citation)

A distributed firewall is utilized in conjunction with a memory-mapped serial communications interface such as that defined by the IEEE 1394 specification to permit secure data transmission between selected nodes over the interface. The distributed firewall incorporates security managers in the sele ...


10
John L Cain: Optimization of dry etching through the control of helium backside pressure. VLSI Technology, Burns Doane Swecker & Mathis L, April 29, 1997: US05624582 (153 worldwide citation)

In a dry non-isotropic etching process, backside cooling by helium controls the rate and uniformity of etching in a thermal silicon layer, the taper of profiles etched into silicon dioxide layers, and the dimension and uniformity of etched structures in a polycide or polysilicon layer, on the surfac ...