1
Gary D McCormack, Ronald F Talaga Jr: Multiple channel adaptive data recovery system. Vitesse Semiconductor Corporation, Christie Parker & Hale, October 8, 2002: US06463109 (75 worldwide citation)

A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel ar ...


2
Gary D McCormack, Ronald F Talaga Jr, Ian A Kyles, Angus J McCamant: Adaptive data recovery system and methods. Vitesse Semiconductor Corporation, Christie Parker & Hale, January 23, 2001: US06178213 (70 worldwide citation)

A microprocessor controlled data recovery unit with an adjustable sampling and signal comparison level. The data recovery unit includes a data channel and a monitor channel. The monitor channel samples an incoming data stream in a varying manner. The results of the sampling in the monitor channel ar ...


3
John P Mullaney, Gary M Lee: High speed cross point switch routing circuit with word-synchronous serial back plane. Vitesse Semiconductor Corporation, Christie Parker & Hale, April 23, 2002: US06377575 (68 worldwide citation)

An asynchronous serial crosspoint switch is word synchronized to each of a number of transceiver circuits. The crosspoint switch circuit generates both a master bit clock and a master word clock signal. A transceiver circuit recovers the master bit clock signal from an incoming high-speed serial dat ...


4
Gary McCormack, Ian A Kyles, Angus J McCamant, Norbert J Seitz, Richard R Suter: Crosspoint switch with switch matrix module. Vitesse Semiconductor Corporation, Christie Parker & Hale, September 20, 2005: US06946948 (54 worldwide citation)

A crosspoint switch including a switch matrix modules and programming features. A switch matrix modules include input lines tied to inputs of the switch through precompensation networks. The programming features include user initialization states and reduced and grouping command configuration operat ...


5
Satish Sridharan, Michael Jarchi, Timothy Coe: Product code based forward error correction system. Vitesse Semiconductor Corporation, Christie Parker & Hale, October 26, 2004: US06810499 (52 worldwide citation)

A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decod ...


6
Satish Sridharan, Michael Jarchi: Reed-solomon encoder and decoder. Vitesse Semiconductor Corporation, Christie Parker & Hale, February 17, 2004: US06694476 (45 worldwide citation)

A semi-parallel forward error correction system. In one embodiment the forward error correction system includes a semi-parallel Reed-Solomon encoder and a semi-parallel Reed-Solomon decoder. Information symbols comprised of bytes are provided eight bytes in parallel to an encoder which in parallel f ...


7
Satish Sridharan, Michael Jarchi: Product code based forward error correction system. Vitesse Semiconductor Corporation, Christie Parker & Hale, May 18, 2004: US06738942 (37 worldwide citation)

A multidimensional forward error correction system. Transmitted data is encoded by an encoder in multiple dimensions. The decoding of received data by a decoder is performed in multiple passes, with corrected data rewritten into memory. The encoder in one embodiment comprises a parallel column decod ...


8
Ira Deyhimy, Robert N Deming, William C Terrell, David W Hedges: Method and apparatus for controlling clock skew. Vitesse Semiconductor Corporation, Irell & Manella, April 20, 1993: US05204559 (35 worldwide citation)

A circuit for controlling clock skew has a plurality of delay elements placed in each of the clock output paths in a clock distribution circuit. The delay elements may be selectively switched into or out of each clock output path in order to adjust the delays of each clock output path so that the sk ...


9
Namakkal S Sambamurthy, Devendra K Tripathi, Alak K Deb, Linh Tien Truong, Praveen D Kumar: Media access control architectures and network management systems. Vitesse Semiconductor Corporation, Beyer Weaver & Thomas, May 21, 2002: US06393489 (34 worldwide citation)

Disclosed is a media access controller for transferring data along a computer network. The media access controller includes a transmit media access controller that is configured to process out-going packet data received from an upper layer for transmission to a lower layer. A receive media access co ...


10
Thomas Aakjer: Fuses for memory repair. Vitesse Semiconductor Corporation, Klein O Neill & Singh, November 23, 2010: US07839707 (32 worldwide citation)

Structures for fuses to control repair of multiple memories embedded on an integrated circuit are provided along with methods of use. A set of fuses is shared to control repair of a plurality of memories. Some of the fuses are associated with a memory to be repaired. Others of the fuses identify how ...