1
Nai Shung Chang: Feedback system for accomodating different memory module loading. Via Technologies, J C Patents, June 1, 2004: US06745275 (133 worldwide citation)

A feedback system capable of accommodating different memory module loading. The feedback system utilizes the signal received by the data strobe feedback pin of a control chipset to simulate or to obtain memory module loading information so that timing of the data signal and data strobe signal can be ...


2
Rochelle L Stortz, Raymond A Bertram: System and method for determination of a horizontal minimum of digital values. VIA Technologies, Gary Stanford, James W Huffman, February 11, 2014: US08650232 (102 worldwide citation)

A system for fast determination of a horizontal minimum of multiple digital values including a difference circuit and a compare circuit. The difference circuit may include first and second adders in which the first adder compares upper bits of a first digital value with upper bits of a second digita ...


3
Nai Shung Chang, Chia Hsing Yu, Chia Hsin Chen: Motherboard with reduced power consumption. VIA Technologies, J C Patents, February 28, 2006: US07007175 (100 worldwide citation)

A motherboard with reduced power consumption is disclosed. The motherboard has a memory module slot, a DDR termination array, and a control chip. The DDR termination array couples to the memory module slot and provides a termination resistor that has one terminal coupled to a voltage source. The con ...


4
Chun Chih Yang, Yung Chung Chang, Shu Tzu Wang: Method of placement and routing for an array device. Via Technologies, J C Patents, October 15, 2002: US06467072 (97 worldwide citation)

The invention provides a method of placement and routing for an array device in an integrated circuit (IC). In the method, a schematic script file used to describe placement for the array device is created according to a netlist and an array structure specification. The schematic script file is load ...


5
Kwun Yao Ho, Moriss Kung, Terry Ku, Andy Liao: Integrated circuit package with a balanced-part structure. Via Technologies, February 13, 2007: US07176559 (79 worldwide citation)

An integrated circuit package includes a balanced-part structure. The condition of thermal stress of chips connected on a substrate decides the amount, locations, weights, and the material of at least a balanced-part fastened on a substrate. The balanced-part is fastened on the substrate to balance ...


6
Hsueh Chung Shelton Lu, Kenny Chang, Jimmy Huang: Flip-chip bump arrangement for decreasing impedance. Via Technologies, Troxell Law Office PLLC, January 20, 2004: US06680544 (75 worldwide citation)

A bump arrangement of a flip-chip is disclosed. The bump arrangement comprises: a conductive bumps array formed at a core region of the flip-chip, a first ring of conductive bumps surrounding the conductive bumps array, a second ring surrounding the first ring, a third ring surrounding the second ri ...


7
Chi Hsing Hsu: Flip-chip die and flip-chip package substrate. VIA Technologies, Jiang Chyun IP Office, March 1, 2005: US06861740 (74 worldwide citation)

A flip-chip die and a flip-chip package substrate. The flip-chip die has an active surface containing a plurality of core power/ground pads, at least one signal pad rings, at least one power pad rings and at least one ground pad rings. The core power/ground pads are located in the central region of ...


8
Chi Hsing Hsu: Flip chip package carrier. VIA Technologies, J C Patents, October 26, 2004: US06809262 (66 worldwide citation)

A flip chip package carrier having a substrate is disclosed. The substrate has a surface with a plurality of bonding pads for connecting with a chip. A solder mask layer covers the substrate. The solder mask layer has a solder mask opening that exposes the bonding pads. Furthermore, a solder layer c ...


9
Chi Hsing Hsu: Quad flat no-lead chip carrier. VIA Technologies, Jiang Chyun IP Office, April 19, 2005: US06882057 (63 worldwide citation)

A quad flat no-lead chip carrier for a wire-bonded chip package is provided. The chip carrier comprises a conductive plate, a plurality of conductive columns and a plurality of dielectric walls. A chip is attached to the conductive plate. The conductive plate furthermore has a plurality of columnar ...


10
Jyhfong Lin, Shan Shan Lee, Yuwen Swei: Low-voltage, low-jitter voltage controlled oscillator. VIA Technologies, J C Patents, Jiawei Huang, March 28, 2000: US06043719 (61 worldwide citation)

A low-voltage, low-jitter voltage controlled oscillator according to the invention includes a plurality of delay units electrically connected in series to form a closed loop circuit. Each delay unit has a symmetric differential structure constituted by a plurality of MOS FETs. Furthermore, only two ...