1
Brent W Miller, William W Walker, Laurence H Cooke: Scannable latch system and method. Vertex Semiconductor Corporation, A C Smith, Greg T Sueoka, July 14, 1992: US05130568 (113 worldwide citation)

A scannable latch system comprises a plurality of scannable latches and clock driver circuit that allow at-speed testing of integrated circuits. Each scannable latch comprises a master latch, a slave latch and an auxiliary latch. The master latch is a two input latch capable of receiving data from t ...


2
Michael A Ang: GTL to CMOS level signal converter, method and apparatus. Vertex Semiconductor Corporation, Limbach & Limbach, April 11, 1995: US05406143 (6 worldwide citation)

A GTL signal to CMOS level signal converter has a sense amplifier to receive the GTL signal and a clock signal and generate a first signal in response thereto. A buffer has a plurality of clocked stages for receiving the clock signal and the first signal and for generating the CMOS signal. A clock g ...


3
Andrea Nguyen, Joe Yeun, Charles Stearns: Memory buffer having selective flush capability. Vertex Semiconductor Corporation, Ronald L Yin, Limbach & Limbach, May 23, 1995: US05418755 (4 worldwide citation)

A write buffer having selective flush is disclosed. The write buffer has address buffers and associated data buffers and comparators. During a "sneak read" operation, the address of the read operation is compared to the address signals stored in each of the address buffers. If a match is found, the ...


4
Nguyen Andrea, Yeun Joe, Stearns Charles: Memory buffer having selective flush capability. Vertex Semiconductor Corporation, YIN Ronald L, January 19, 1995: WO/1995/002248

A write buffer (10) having selective flush is disclosed. The write buffer (10) has address buffers (50) and associated data buffers (52) and comparators (54). During a 'sneak read' operation, the address of the read operation is compared to the address signals stored in each of the address buffers ( ...