1
Chen Chung Hsu: Three-dimensional multichip package. United Microelectronics Corporation, George O Saile, Wolmar Stoffel, January 2, 1996: US05481133 (350 worldwide citation)

A multichip array package for IC devices with a master semiconductor device supporting and electrically interconnected with a stacked array of subordinate devices. The interconnection structure has a peripheral row of contact pads on the master device. The subordinate devices each have a peripheral ...


2
Chen Chung Hsu: Three-dimensional multichip package and methods of fabricating. United Microelectronics Corporation, George O Saile, Wolmar J Stoffel, January 10, 1995: US05380681 (259 worldwide citation)

A process for fabricating a three-dimensional multi-chip array package wherein master semiconductor substrate is formed having a peripheral inner row of contact pads and a peripheral outer row of terminal pads. A plurality of subordinate semiconductor substrates are formed provided with a peripheral ...


3
Meng Jin Tsai, Water Lur, Chin Lai Chen: Method for forming shallow trench isolation. United Microelectronics, Harness Dickey & Pierce, January 27, 1998: US05712185 (229 worldwide citation)

A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resi ...


4
Chen Chung Hsu: Trench method for three dimensional chip connecting during IC fabrication. United Microelectronics Corporation, William H Wright, May 6, 1997: US05627106 (218 worldwide citation)

A new method of connecting three-dimensional integrated circuit chips using trench technology is described. Semiconductor device structures are provided in and on the top side of a semiconductor substrate of a first and a second three-dimensional integrated circuit chip. Deep trenches are etched int ...


5
Heng S Huang: Process for producing non-volatile memory devices having closely spaced buried bit lines and non-overlapping code implant areas. United Microelectronics Corporation, George O Saile, Wolmar J Stoffel, January 3, 1995: US05378649 (207 worldwide citation)

This inventions provides a method to form metal lines with smaller line pitches than is possible using the conventional photolithographic single coating process. This invention provides for a double photolithographic process where the surface is coated, exposed and developed twice to form two sets o ...


6
Chiung Sheng Hsiung, Wen Yi Hsieh, Water Lur: Copper damascene technology for ultra large scale integration circuits. United Microelectronics, Harness Dickey & Pierce, January 16, 2001: US06174812 (205 worldwide citation)

A copper-palladium alloy damascene technology applied to the ultra large scale integration (ULSI) circuits fabrication is disclosed. First, a TaN barrier is deposited over an oxide layer or in terms of the inter metal dielectric (IMD) layer. Then a copper-palladium seed is deposited over the TaN bar ...


7
Chih Chien Liu, Kuen Jian Chen, Yu Hao Chen, J Y Wu, Water Lur, Shih Wei Sun: Multi-step high density plasma chemical vapor deposition process. United Microelectronics, Rabin & Champagne P C, October 19, 1999: US05968610 (199 worldwide citation)

A method for depositing dielectric material into gaps between wiring lines in the formation of a semiconductor device includes the deposition of three oxide layers using high density plasma chemical vapor deposition (HDPCVD). A first HDPCVD step is carried out while keeping the substrate unbiased to ...


8
Min Yi Lin: Dual damascene interconnect structure with reduced parasitic capacitance. United Microelectronics, Winston Hsu, October 2, 2001: US06297554 (191 worldwide citation)

An improved structure of a dielectric layer between two adjacent copper wiring lines is disclosed. The dielectric layer is composed of silicon oxide and the adjacent copper wiring lines are formed using a dual damascene process. The structure of the dielectric layer according to the present inventio ...


9
Min Chih Hsuan, Cheng Te Lin: Multi-chip chip scale package. United Microelectronics, May 29, 2001: US06239367 (186 worldwide citation)

A multi-chip chip scale package. The package has a film carrier whereby two chips with different sizes can be disposed on the same film carrier. A flip chip technique is used to arrange each chip on each side of the film carrier face to face. A bump is formed on each chip to electrically connect wit ...


10
Chih Chien Liu, Juan Yuan Wu, Water Lur, Shih Wei Sun: Method of gap filling. United Microelectronics, Oblon Spivak McClelland Maier & Neustadt P C, March 20, 2001: US06203863 (159 worldwide citation)

A method of gap filling by using HDPCVD. On a substrate having a conductive structure, a first oxide layer is formed to protect the conductive structure. While forming the first oxide layer no bias is applied. An argon flow with a high speed of etching/deposition is provided to form a second oxide l ...