1
Oleg Siniaguine, Sergey Savastiouk: Package of integrated circuits and vertical integration. Tru Si Technologies, Michael Shenker, Skjerven Morrill MacPherson, November 27, 2001: US06322903 (483 worldwide citation)

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the via ...


2
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, May 23, 2006: US07049170 (292 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...


3
Oleg Siniaguine, Sergey Savastiouk: Packaging of integrated circuits and vertical integration. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, February 17, 2004: US06693361 (275 worldwide citation)

A first level packaging wafer is made of a semiconductor or insulating material. The bumps on the wafer are made using vertical integration technology, without solder or electroplating. More particularly, vias are etched part way into a first surface of the substrate. Metal is deposited into the via ...


4
Oleg Siniaguine: Integrated circuit structures with a conductor formed in a through hole in a semiconductor substrate and protruding from a surface of the substrate. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, April 19, 2005: US06882030 (273 worldwide citation)

To fabricate contacts on a wafer backside, openings (124) are formed in the face side of the wafer (104). A dielectric layer (140) and some contact material (150), e.g. metal, are deposited into the openings. Then the backside is etched until the contacts (150C) are exposed and protrude out. The pro ...


5
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Packaging substrates for integrated circuits and soldering methods. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, June 13, 2006: US07060601 (270 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...


6
Oleg Siniaguine: Integrated circuits and methods for their fabrication. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, May 25, 2004: US06740582 (270 worldwide citation)

To fabricate back side contact pads that are suitable for use in a vertical integrated circuit, vias are made in the face side of a wafer, and dielectric and contact pad metal are deposited into the vias. Then the wafer back side is etched until the metal is exposed. When the etch exposes the insula ...


7
Patrick B Halahan, Oleg Siniaguine: Semiconductor structures having multiple conductive layers in an opening, and methods for fabricating same. Tru Si Technologies, Michael Shenker, Skjerven Morrill, December 24, 2002: US06498381 (126 worldwide citation)

In some embodiments, a circuit structure comprises a semiconductor substrate, an opening passing through the substrate between a first side of the substrate and a second side of the substrate, and a plurality of conductive layers in the opening. In some embodiments, one conductive layer provides an ...


8
Patrick B Halahan: Structures having a substrate with a cavity and having an integrated circuit bonded to a contact pad located in the cavity. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, September 7, 2004: US06787916 (116 worldwide citation)

Semiconductor dies are bonded to contact pads formed in a substrate's cavity. Vias through the substrate open into the cavity. Conductive lines passing through the vias connect the contact pads in the cavity to contact pads on another side of the substrate. A passage in the substrate opens into ...


9
Patrick A Halahan, Sam Kao, Bosco Lan, Sergey Savastiouk, Oleg Siniaguine: Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, May 24, 2005: US06897148 (80 worldwide citation)

A through hole (114) is formed in a wafer (104) comprising a semiconductor substrate (110). A seed layer (610) is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor (810) is electroplated into t ...


10
Sergey Savastiouk, Patrick B Halahan, Sam Kao: Packaging substrates for integrated circuits and soldering methods. Tru Si Technologies, Michael Shenker, MacPherson Kwok Chen & Heid, April 25, 2006: US07034401 (73 worldwide citation)

A packaging substrate (310) includes a semiconductor interposer (120) and at least one other intermediate substrate (110), e.g. a BT substrate. The semiconductor interposer has first contact pads (136C) attachable to dies (124) above the interposer, and second contact pads (340) attachable to circui ...