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Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (11 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


2
Buynoski Matthew S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H: Self assembly of conducting polymer for formation of polymer memory cell. Advanced Micro Devices, Buynoski Matthew, S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H, sDRAKE Paul S, May 6, 2005: WO/2005/041319 (1 worldwide citation)

The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer (22) self assembles relative to a conductive electrode (26). The process affords self-assembly such that a sho ...


3
Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010892

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


4
Tripsas Nicholas H, Buynoski Matthew, Okoroanyanwu Uzodinma, Pangrle Suzette K: Planar polymer memory device. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Okoroanyanwu Uzodinma, Pangrle Suzette, K, sCOLLOPY Daniel R, December 16, 2004: WO/2004/109803

The present invention provides a planar polymer memory device (100) that can operate as a non-volatile memory device. A planar polymer memory device (100) can be formed with two or more electrodes and an electrode extension associated with one electrode, wherein a selectively conductive medium and d ...


5
Sokolik Igor, Kingborough Richard P, Leonard William G, Yudanov Nicolay F, Pangrle Suzette K, Tripsas Nicholas H, Ngo Minh Van: System and method for processing an organic memory cell. Spansion, Advanced Micro Devices, Sokolik Igor, Kingborough Richard P, Leonard William G, Yudanov Nicolay F, Pangrle Suzette K, Tripsas Nicholas H, Ngo Minh Van, JAIPERSHAD Rajendra, May 3, 2007: WO/2007/050270

A system (200) and method are disclosed for processing an organic memory cell. An exemplary system (200) can employ an enclosed processing chamber (202), a passive layer formation component (204) operative to form a passive layer on a first electrode, and an organic semiconductor layer formation com ...


6
Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A: Protection of active layers of memory cells during processing of other elements. Spansion, Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A, LAM Christine S, May 18, 2006: WO/2006/053163

A method of fabricating an electronic structure by providing a conductive layer (102), providing a dielectric layer (100) over the conductive layer (102), providing first and second openings (104, 106) through the dielectric layer (100), providing first and second conductive bodies (108, 110) in the ...



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