1
Tomoharu Tanaka, Gertjan Hemink: Multi-state EEPROM having write-verify control circuit. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, October 29, 1996: US05570315 (878 worldwide citation)

An EEPROM having a memory cell array in which electrically programmable memory cells are arranged in a matrix and each of the memory cells has three storage states, includes a plurality of data circuits for temporarily storing data for controlling write operation states of the plurality of memory ce ...


2
Ken Takeuchi, Tomoharu Tanaka: Semiconductor device and memory system. Kabushiki Kaisha Toshiba, Banner & Witcoff, April 4, 2000: US06046935 (872 worldwide citation)

A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data item ...


3
Tetsuo Endoh, Yoshiyuki Tanaka, Seiichi Aritome, Riichiro Shirota, Susumu Shuto, Tomoharu Tanaka, Gertjan Hemink, Toru Tanzawa: Non-volatile semiconductor memory device and method of programming a non-volatile memory cell to a predetermined state. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, June 30, 1998: US05774397 (568 worldwide citation)

A non-volatile semiconductor memory device includes a semiconductor substrate, a memory cell including source and drain regions formed in a surface region of the semiconductor substrate, and a first gate insulating film, a charge storage layer, a second gate insulating film, and a control gate seque ...


4
Makoto Jinno: Manipulator. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt P C, May 3, 2005: US06889116 (543 worldwide citation)

A manipulator comprises an operation command unit provided with an attitude adjusting unit and an end effector control unit, a connecting unit having one end connected to the operation command unit, a working unit connected to the other end of the connecting unit and provided with an end effector an ...


5
Ken Takeuchi, Tomoharu Tanaka: Semiconductor device and memory system. Kabushiki Kaisha Toshiba, Banner & Witcoff, May 11, 1999: US05903495 (412 worldwide citation)

A semiconductor memory device comprises a memory cell array having electrically erasable and programmable memory cells arranged in rows and columns, each memory cell capable of storing n-value data (n is 3 or a greater natural number), and a data circuit having m latch circuits for holding data item ...


6
Masatoshi Nakai, Takeshi Hagio: Multiangle block reproduction system. Kabushiki Kaisha Toshiba, Pillsbury Madison & Sutro, December 7, 1999: US05999698 (363 worldwide citation)

In reproduction of a predetermined title recorded on an optical disk, when multiangle video images are recorded on the optical disk, an angle mark having a form of a camera is turned on. During reproduction of this title, when reproduction reaches a multiangle video image recorded portion, the angle ...


7
Roberto Cipolla, Yasukazu Okamoto, Yoshinori Kuno: 3D human interface apparatus using motion recognition based on dynamic image processing. Kabushiki Kaisha Toshiba, Foley & Lardner, December 3, 1996: US05581276 (361 worldwide citation)

A 3D human interface apparatus using a motion recognition based on a dynamic image processing in which the motion of an operator operated object as an imaging target can be recognized accurately and stably. The apparatus includes: an image input unit for entering a plurality of time series images of ...


8
Masaki Momodomi, Fujio Masuoka, Riichiro Shirota, Yasuo Itoh, Kazunori Ohuchi, Ryouhei Kirisawa: Electrically erasable programmable read-only memory with NAND cell structure. Kabushiki Kaisha Toshiba, Oblon Spivak McClelland Maier & Neustadt, September 25, 1990: US04959812 (351 worldwide citation)

An erasable programmable read-only memory with NAND cell structure is disclosed which has memory cells provided on a N type substrate. The memory cells are divided into NAND cell blocks each of which has a series array of memory cell transistors. Each of the transistors has a floating gate, a contro ...


9
Shinichi Kikuchi, Takeo Arafune, Tetsuya Kitamura, Hideki Mimura, Kazuhiko Taira, Yuzo Tamada: Recording medium on which a data containing navigation data is recorded, a method and apparatus for reproducing a data according to navigation data, a method and apparatus for recording a data containing navigation data on a recording. Kabushiki Kaisha Toshiba, Pillsbury Madison & Sutro, February 9, 1999: US05870523 (315 worldwide citation)

In a super density optical disk for storing video data, wherein data video is compressed to packs defined in MPEG and trains of the packs are stored in a video object unit. The video object unit includes a navigation pack which is placed at the head of the pack train. In a data cell, a plurality of ...


10
Mutsunori Igarashi, Takashi Mitsuhashi, Masami Murakata, Masaaki Yamada, Fumihiro Minami, Toshihiro Akiyama, Takahiro Aoki: Semiconductor integrated circuit device, semiconductor integrated circuit wiring method, and cell arranging method. Kabushiki Kaisha Toshiba, Foley & Lardner, July 17, 2001: US06262487 (313 worldwide citation)

There are disclosed a semiconductor integrated circuit device, a semiconductor integrated circuit wiring method and a cell arranging method, which can reduce delay in a semiconductor integrated circuit and improve noise resistibility., achieve facility of wiring design, and reduce production cost.



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