1
Kenji Kimura, Kohji Ishikawa, Naoaki Narumi: Semiconductor memory test equipment. Nippon Telegraph & Telephone Public, Takeda Riken Kogyo Kabushiki Kaisha, Staas & Halsey, January 18, 1983: US04369511 (84 worldwide citation)

A semiconductor memory test equipment which reads out a memory under test by an address from a pattern generator and compares the read-out data with an expected value by a comparator, and in which a block mask memory is read out by a portion of the address and the comparing operation of the comparat ...


2
Shigeru Sugamori: IC Tester. Takeda Riken, Staas & Halsey, January 29, 1985: US04497056 (73 worldwide citation)

An IC tester supplies test pattern signal to an IC being tested and compares response signals therefrom with an expected-value pattern signal to determine whether the IC is acceptable or not. During the test, the IC being tested is severed by a separator means from the drivers, for producing the tes ...


3
Kenji Kimura, Shigeru Sugamori, Kohji Ishikawa, Naoaki Narumi: Semiconductor memory device test apparatus. Nippon Telegraph & Telephone Public, Takeda Riken Kogyo Kabushikikaisha, Staas & Halsey, November 8, 1983: US04414665 (70 worldwide citation)

A memory device under test is accessed by an address generated by a pattern generator to write therein data and to read the data out to be compared with expected data, and the comparison result is stored in the fault-address memory by the same address after reading out therefrom the content of the a ...


4
Masao Shimizu, Takashi Tokuno, Kohji Ishikawa, Naoaki Narumi, Osamu Ohguchi: Test pattern generating apparatus. Nippon Telegraph and Telephone Public Corporation, Takeda Riken Kogyo Kabushikikaisha, Staas & Halsey, October 6, 1981: US04293950 (64 worldwide citation)

A test pattern generating apparatus in which a microprogram describing a test pattern to be generated is read for interpretation and execution, address and data patterns are generated by arithmetic operations and a memory control signal is produced, the address and data patterns and the memory contr ...


5
Masakazu Nakamura: Waveform display apparatus. Takeda Riken Kogyo Kabushiki Kaisha, Staas & Halsey, August 7, 1984: US04464656 (59 worldwide citation)

An analog waveform is sampled and converted into a digital form corresponding to the number of picture elements in the direction of main scanning of a raster scanning type display unit. The digital value thus obtained is stored in a memory which has the same number of addresses as the above-mentione ...


6
Kempei Suzuki, Yushi Iwanaga, Hiroshi Sato, Kohei Sato, Noriyuki Igarashi, Shinichi Koya: IC test equipment. Takeda Riken, Staas & Halsey, September 8, 1987: US04691831 (53 worldwide citation)

An IC element supplied to a testing station is guided by a rail and a guide member to move by its own weight. At least one of the rail and guide member has built therein plate-shaped ceramic heater or plate-shaped silicone rubber heater. The guide member urges the IC element against the rail to heat ...


7
Tetsuo Aoki: Data transfer system. Takeda Riken, Staas & Halsey, December 4, 1984: US04486750 (52 worldwide citation)

Control side equipment and at least one equipment under control are commonly interconnected via a data line and a strobe line. The equipment under control is provided with means for retaining the logic of a strobe pulse when it is received from a strobe line. When the control side equipment has set ...


8
Kenji Yoshida: Delay pulse generating circuit. Takeda Riken, Staas & Halsey, March 12, 1985: US04504749 (44 worldwide citation)

A delay signal generating circuit includes feedback loops and components for selectively setting the delay time of a delay unit in one of the loops. The circuit can be used to provide an adjustable delay to a signal being propagated therethrough, and the delay unit can be bypassed.


9
Junji Nishiura: Logic test system permitting test pattern changes without dummy cycles. Takeda Riken Kogyo Kabushikikaisha, Staas & Halsey, January 26, 1982: US04313200 (41 worldwide citation)

A system for testing logical devices, in which a pattern file is used to store numerous test patterns, each of which includes both an input pattern, which is provided as an input to the device under test, and an expected value pattern, which is compared with the actual output of the device under tes ...


10
Kunio Takeuchi: IC tester. Takeda Riken, Staas & Halsey, June 11, 1985: US04523312 (30 worldwide citation)

An IC tester has a plurality of drivers for delivering test pattern signals through connector lines to corresponding terminal pins of an IC being tested. Outputs supplied from the IC being tested in response to the test pattern signals are delivered back through the connector lines to comparators co ...