1
Tsu Jae King, Victor Moroz: Segmented channel MOS transistor. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, July 24, 2007: US07247887 (303 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


2
Wai Yan Ho, Hongbo Tang: Method and system for layout verification of an integrated circuit design with reusable subdesigns. Synopsys, Wagner Murabito & Hao, December 28, 1999: US06009251 (262 worldwide citation)

A method and system for performing layout verification on an integrated circuit (IC) design using reusable subdesigns. Many custom designed integrated circuits are designed and fabricated using a number of computer implemented automatic design processes. Within these processes, a high level design l ...


3
Jonathan Goldman, Garry Saperstein: Method and system for user authorization over a multi-user computer system. Synopsys, Wagner Murabito & Hao, November 4, 1997: US05684951 (224 worldwide citation)

A method and system for performing user authorization in a multi-user computer system. The novel method has particular application to the multi-user internet protocol. Within the system, an application contains a list of registered users. For each registered user, the application stores a user ident ...


4
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, March 13, 2007: US07190050 (223 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


5
Tsu Jae King, Victor Moroz: Integrated circuit on corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, May 5, 2009: US07528465 (209 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


6
Tsu Jae King Liu, Qiang Lu: Enhanced segmented channel MOS transistor with narrowed base regions. Synopsys, Silicon Valley Patent Group, Edward S Mao, March 24, 2009: US07508031 (205 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably produced ...


7
Tsu Jae King, Victor Moroz: Method of IC production using corrugated substrate. Synopsys, Bever Hoffman & Harms, Jeanette S Harms, September 4, 2007: US07265008 (201 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


8
Tsu Jae King Liu, Qiang Lu: Enhanced segmented channel MOS transistor with high-permittivity dielectric isolation material. Synopsys, Silicon Valley Patent Group, Edward S Mao, October 20, 2009: US07605449 (200 worldwide citation)

By forming MOSFETs on a substrate having pre-existing ridges of semiconductor material (i.e., a “corrugated substrate”), the resolution limitations associated with conventional semiconductor manufacturing processes can be overcome, and high-performance, low-power transistors can be reliably and repe ...


9
Abbas El Gamal, David P Marple, Justin M Reyneri: CAD and simulation system for targeting IC designs to multiple fabrication processes. Synopsys, Brian D Ogonowsky, Skjerven Morrill MacPherson Franklin & Friel, May 19, 1998: US05754826 (198 worldwide citation)

Using the present invention, only a single design and development process needs to be conducted for ICs fabricated using a number of different fabrication processes. In one embodiment of this process, the IC is first designed on a CAD system using a generic Cell Based Architecture (CBA) library. Thi ...


10
William Wai Yan Ho: Layer-based rule checking for an integrated circuit layout. Synopsys, Wagner Murabito & Hao, April 23, 2002: US06378110 (186 worldwide citation)

A computer implemented method for verifying a physical layout of an integrated circuit design for a semiconductor chip. The physical layout is specified in terms of a plurality of layers used to fabricate the chip. Initially, a pre-defined set of rules are stored in memory. These rules are used to s ...



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