1
Itzic Cohen, Ori Tirosh, Kobi Danon, Shmulik Hadas: Recovery while programming non-volatile memory (NVM). Spansion Isreal, Ettan Mehulal Law Group, May 17, 2011: US07945825 (130 worldwide citation)

Disclosed are methods and circuits for performing recovery associated with programming of non-volatile memory (NVM) array cells. According to embodiments, there are provided methods and circuits for programming NVM cells, including: (1) erasing NVM array cells; (2) loading an SRAM with user data; (3 ...


2
Kobi Danon, Shai Eisen, Marcelo Krygier: Operation of a non-volatile memory array. Spansion Israel, Eitan Mehulal Law Group, April 12, 2011: US07924628 (105 worldwide citation)

A cache programming operation which requires 2 SRAMs (one for the user and one for the array) may be combined with a multi-level cell (MLC) programming operation which also requires 2 SRAMs (one for caching the data and one for verifying the data), using only a total of two SRAMs (or buffers). One o ...


3
Darlene Hamilton, Ed Hsia, Pau Ling Chen: Multi bit program algorithm. Spansion, Eschweiler & Associates, May 2, 2006: US07038950 (105 worldwide citation)

Methods of programming NEW data into unprogrammed bits of a group of memory cells is provided. The method applies an interactive programming algorithm that individually verifies and programs the NEW data, reference (REF) data, and existing or OLD data. OLD data is separately verified to a compensate ...


4
Ed Hsia, Darlene Hamilton, Alykhan Madhani, Kenneth Yu: Method of determining voltage compensation for flash memory devices. Spansion, Eschweiler & Associates, October 21, 2008: US07440333 (96 worldwide citation)

The present invention determines or identifies programming variations for different groups within an array or memory device that properly program memory cells within the respective groups. Then, during programming operations for a given memory cell, programming voltages are applied according to the ...


5
Zhigang Wang, Nian Yang, Zhizheng Liu: Method of programming a flash memory device using multilevel charge storage. Spansion, Renner Otto Boisselle & Sklar, May 9, 2006: US07042766 (93 worldwide citation)

Disclosed is a method of programming a flash memory device to store an amount of charge corresponding to one of a plurality of charged program states. The method can include pulsing the memory device with program voltages including at least a gate voltage. If the gate voltage is greater than or equa ...


6
Fatima Bathul, Darlene Hamilton, Masato Horiike: Multi-level ONO flash program algorithm for threshold width control. Spansion, Eschweiler & Associates, October 31, 2006: US07130210 (88 worldwide citation)

Methods of programming a wordline of multi-level flash memory cells (MLB) having three or more data levels per bit corresponding to three or more threshold voltages are provided. The present invention employs an interactive program algorithm that programs the bits of the wordline of memory cells in ...


7
Yano Masaru, Arakawa Hideki, Shiraiwa Hidehiko: Semiconductor device and operation control method for same. Spansion, Spansion Japan, September 12, 2007: EP1833091-A1 (87 worldwide citation)

A semiconductor device includes: a semiconductor substrate; word lines; global bit lines; inversion gates that form inversion layers serving as local bit lines in the semiconductor substrate, the inversion layers being electrically connected to the global bit lines; and a memory cell using the inver ...


8
Walter Allen, Robert France: Memory array search engine. Spansion, Turocy & Watson, July 12, 2011: US07979667 (79 worldwide citation)

Systems and/or methods that facilitate a search of a memory component(s) to locate a desired logical block address (LBA) associated with a memory location in a memory component are presented. Searches to locate a desired LBA(s) in a memory component(s) associated with a processor component are offlo ...


9
Nicholas H Tripsas, Suzette Pangrle: Memory device with a selection element and a control line in a substantially similar layer. Spansion, Amin Turocy & Calvin, June 24, 2008: US07391064 (78 worldwide citation)

The invention facilitates manufacture of semiconductor memory components by reducing the number of layers required to implement a semiconductor memory device. The invention provides for a selection element to be formed in the same layer as one of the control lines (e.g. one of the wordline and bitli ...


10
Arvind Halliyal, Mark T Ramsbey, Hidehiko Shiraiwa, Jean Y Yang: Integrated ONO processing for semiconductor devices using in-situ steam generation (ISSG) process. Spansion, Renner Otto Boisselle & Sklar, October 3, 2006: US07115469 (69 worldwide citation)

A process for fabrication of a semiconductor device including an ONO structure as a component of a flash memory device, comprising forming the ONO structure by providing a semiconductor substrate having a silicon surface; forming a first oxide layer on the silicon surface; depositing a silicon nitri ...