1
Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T, DRAKE Paul S, May 6, 2005: WO/2005/041024 (4 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


2
Lepak Kevin Michael, Smaus Gregory William, Hughes William A, Kalyanasundharam Vydhyanathan: Coherent dram prefetcher. Advanced Micro Devices, Lepak Kevin Michael, Smaus Gregory William, Hughes William A, Kalyanasundharam Vydhyanathan, DRAKE Paul S, April 30, 2009: WO/2009/054959 (1 worldwide citation)

A system and method for obtaining coherence permission for speculative prefetched data. A memory controller stores an address of a prefetch memory line in a prefetch buffer. Upon allocation of an entry in the prefetch buffer a snoop of all the caches in the system occurs. Coherency permission inform ...


3
Smaus Gregory William, Tuuk Michael, Tupuri Raghuram S: Call return stack way prediction repair. Advanced Micro Devices, Smaus Gregory William, Tuuk Michael, Tupuri Raghuram S, DRAKE Paul S, February 15, 2007: WO/2007/019001

A mechanism for repairing way mispredictions in a cache. An instruction cache (16) in a processor (10) is coupled to receive a fetch address (236) and a corresponding way prediction (280). A return address stack (230) is configured to store a return address corresponding to a fetched branch instruct ...