1
Namakkal S Sambamurthy, Woo Ping Lai, John P VanGilder: Apparatus and method for full-duplex ethernet communications. Seeq Technology Incorporated, D Alessandro Frazzini & Ritchie, May 10, 1994: US05311114 (118 worldwide citation)

A downward compatible full-duplex 10Base-T ethernet transceiver associated with either the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and d ...


2
Gust Perlegos, Tsung Ching Wu: MOS floating gate memory cell containing tunneling diffusion region in contact with drain and extending under edges of field oxide. Seeq Technology, Lyon & Lyon, April 18, 1989: US04822750 (64 worldwide citation)

A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel o ...


3
Anil Gupta: Charge pump for providing programming voltage to the word lines in a semiconductor memory array. Seeq Technology, Lyon & Lyon, April 16, 1985: US04511811 (63 worldwide citation)

A charge pump for providing programming voltages to the word lines of a semiconductor memory array is disclosed. The charge pump, configured as a combination of enhancement and native MOS transistors, prevents DC current from flowing from the source of the programming voltage to ground through unsel ...


4
William W Ip, Gust Perlegos: CMOS eprom sense amplifier. Seeq Technology, Lyon & Lyon, February 16, 1988: US04725984 (60 worldwide citation)

Individual CMOS floating-gate memory cells capable of storing data are arranged in an array structure and selected with horizontal and vertical access lines. Current flow through the array cells is measured, amplified, and then compared with an unprogrammed cell using the sense amplifier of the pres ...


5
Te Long Chiu: Method of fabricating an MOS memory array having electrically-programmable and electrically-erasable storage devices incorporated therein. SEEQ Technology, Lyon & Lyon, January 1, 1985: US04490900 (57 worldwide citation)

A method for fabricating an MOS memory array is disclosed, wherein the method includes steps for constructing electrically-programmable and electrically-erasable memory cells (2, 198, 200) in combination with assorted peripheral devices (202, 204, 206) on a semiconductor substrate (8, 71). Tunneling ...


6
Sanjay Mehrotra, Gust Perlegos: Error checking and correction circuitry for use with an electrically-programmable and electrically-erasable memory array. Seeq Technology, Lyon & Lyon, September 16, 1986: US04612640 (56 worldwide citation)

An on-chip checking and correction circuit extends the program/erase endurance of a semi-conductor memory array and catches data retention failures in individual memory cells of the array. For each data byte in the memory array, four parity bits are computed using a modified Hamming Code and stored ...


7
Namakkal S Sambamurthy, Woo Ping Lai, John P VanGilder: Apparatus and method for full-duplex ethernet communications. Seeq Technology, D Alessandro & Ritchie, April 2, 1996: US05504738 (56 worldwide citation)

A downward compatible full-duplex 10Base-T ethernet transceiver associated with both the hub or the remote node in an ethernet network includes generator circuitry for generating a full-duplex-capability signal indicating its full-duplex capability for transmission over the twisted pair link and det ...


8
Gust Perlegos, Tsung Ching Wu: MOS floating gate memory cell and process for fabricating same. Seeq Technology, Lyon & Lyon, October 20, 1987: US04701776 (55 worldwide citation)

A two device floating gate MOS nonvolatile memory cell is disclosed including a floating gate memory device coupled to a select device wherein a thin tunnel dielectric region of insulation material between the substrate and floating gate of the memory device is located in an area above the channel o ...


9
Ting Wah Wong, Raul Adrian Cernea: Current-regulated, voltage-regulated erase circuit for EEPROM memory. Seeq Technology, Lyon & Lyon, December 19, 1989: US04888738 (52 worldwide citation)

A control circuit for erasing EEPROM memory cells is disclosed, including a charge pump having two switched constant current sources driven by opposing clocks. Current produced by the current sources is coupled to a node from where it is used to erase EEPROM memory cells. A switch is provided to iso ...


10
Anil Gupta, George Perlegos: Non-volatile memory cell fuse element. Seeq Technology, Lyon & Lyon, October 8, 1985: US04546454 (49 worldwide citation)

A non-volatile memory cell circuit is used to replace a polysilicon fuse as an enabling element for a redundant row or column of memory cells in a semiconductor memory array. The fuse is divided into read and program sections, allowing a large device to be used for reading and a small device to be u ...