1
Yasunobu Nakase, Koji Nii: Semiconductor memory device capable of generating internal data read timing precisely. Renesas Technology, McDermott Will & Emery, July 6, 2004: US06760269 (193 worldwide citation)

Dummy cells are divided into a plurality of divided dummy columns, and divided dummy bit lines are arranged corresponding to the divided dummy columns. These divided dummy bit lines are provided with dummy sense amplifiers that drive a sense control line transmitting a sense enable signal activating ...


2
Yunfei Ding: Method and system for using a pulsed field to assist spin transfer induced switching of magnetic memory elements. Grandis, Renesas Technology, Strategic Patent Group P C, March 10, 2009: US07502249 (148 worldwide citation)

A method and system for providing and utilizing a magnetic memory are described. The magnetic memory includes a plurality of magnetic storage cells. Each magnetic storage cell includes magnetic element(s) programmable due to spin transfer when a write current is passed through the magnetic element(s ...


3
Tomio Iwasaki, Hiroshi Moriya, Hideyuki Matsuoka, Norikatsu Takaura: Phase change memory and phase change recording medium. Renesas Technology, Antonelli Terry Stout and Kraus, October 24, 2006: US07126149 (147 worldwide citation)

A phase change memory comprises: a substrate; an insulation film formed on a main surface of the substrate; a first electrode deposited on the insulation film; a phase change recording film deposited on the first electrode; and a second electrode deposited on the phase change recording film. The pha ...


4
Shoji Shukuri, Kazuhiro Komori, Katsuhiko Kubota, Kousuke Okuyama: Semiconductor integrated circuit and nonvolatile memory element. Renesas Technology, Antonelli Terry Stout & Kraus, August 3, 2004: US06771538 (146 worldwide citation)

Owing to the above, even with the single-layer gate process such as single-layer polysilicon gate process, it is possible to obtain a semiconductor integrated circuit such as system LSI in which a nonvolatile memory which is excellent in data retention capability is merged and packaged with a DRAM e ...


5
Eugene Youjun Chen, Yiming Huai, Alex Fischer Panchula, Lien Chang Wang, Xiao Luo: Current driven switching of magnetic storage cells utilizing spin transfer and magnetic memories using such cells having enhanced read and write margins. Grandis, Renesas Technology, Strategic Patent Group P C, May 27, 2008: US07379327 (142 worldwide citation)

A method and system for providing a magnetic memory. The magnetic memory includes magnetic storage cells in an array, bit lines, and source lines. Each magnetic storage cell includes at least one magnetic element. The magnetic element(s) are programmable by write currents driven through the magnetic ...


6
Tsukasa Ooishi: Non-volatile semiconductor memory device allowing shrinking of memory cell. Renesas Technology, Buchanan Ingersoll & Rooney PC, April 24, 2007: US07208751 (140 worldwide citation)

Dummy cells are disposed in alignment with memory cells arranged in rows and columns in a memory array. The memory cell includes a variable resistance element and a select transistor having a collector connected to a substrate region and selecting the variable resistance element in response to a row ...


7
Xiao Luo, Eugene Youjun Chen, Lien Chang Wang, Yiming Huai: Method and system for providing a magnetic memory structure utilizing spin transfer. Grandis, Renesas Technology, Strategic Patent Group P C, March 18, 2008: US07345912 (140 worldwide citation)

A method and system for providing a magnetic memory is described. The method and system include providing magnetic memory cells, local and global word lines, bit lines, and source lines. Each magnetic memory cell includes a magnetic element and a selection device connected with the magnetic element. ...


8
Ichikawa Katsuhide, Nagashima Toshio: Power amplification and detection circuit, and transmitter and transceiver each using the same,. Renesas Technology, July 17, 2008: JP2008-167017 (136 worldwide citation)

PROBLEM TO BE SOLVED: To solve a problem where transmission output control can not be sufficiently performed because of the shortage of detection voltage sensitivity of a detection circuit and gain of output power decreases caused by a parasitic component that occurs at a collector terminal of a tra ...


9
Koji Nii, Shigeki Obayashi, Hiroshi Makino, Koichiro Ishibashi, Hirofumi Shinohara: Semiconductor memory device. Renesas Technology, McDermott Will & Emery, March 10, 2009: US07502275 (133 worldwide citation)

Cell power supply lines are arranged for memory cell columns, and adjust impedances or voltage levels of the cell power supply lines according to the voltage levels of bit lines in the corresponding columns, respectively. In the data write operation, the cell power supply line is forced into a float ...


10
Akio Nishida, Yasuko Yoshida, Shuji Ikeda: SRAM having an improved capacitor. Renesas Technology, Antonelli Terry Stout and Kraus, June 27, 2006: US07067864 (125 worldwide citation)

In order to provide a semiconductor integrated circuit device such as a high-performance semiconductor integrated circuit device capable of reducing a soft error developed in each memory cell of a SRAM, the surface of a wiring of a cross-connecting portion, of a SRAM memory cell having a pair of n-c ...