1
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen, Thomas J Holman, Andrew V Anderson, Peter D MacWilliams: High performance cost optimized memory with delayed memory writes. Rambus Incorporated, Intel Corporation, Pennie & Edmonds, June 13, 2000: US06075730 (134 worldwide citation)

A memory device includes an interconnect with control pins and bidirectional data pins. A memory core stores data. A memory interface circuit is connected to the interconnect and the memory core. The memory interface circuit includes a delay circuit to establish a write delay during a memory core wr ...


2
Richard M Barth, Frederick A Ware, Donald C Stark, Craig E Hampel, Paul G Davis, Abhijit M Abhyankar, James A Gasbarro, David Nguyen: High performance cost optimized memory. Rambus Incorporated, Pennie & Edmonds, June 4, 2002: US06401167 (94 worldwide citation)

A memory device includes an interconnect with mask pins and a memory core for storing data. A memory interface circuit is connected between the interconnect and the memory core. The memory interface circuit selectively processes write mask data from the mask pins or precharge instruction signals fro ...


3
Tsern Ely: A memory module including a plurality of integrated circuit memory devices and a plurality of buffer devices in a matrix topology. Rambus Incorporated, Tsern Ely, DENIRO Kirk J, April 5, 2007: WO/2007/038225 (86 worldwide citation)

A memory module includes a plurality of signal paths that provide data to a memory module connector interface from a plurality of respective integrated circuit buffer devices that access data from an associated plurality of integrated circuit memory devices. The memory module forms a plurality of 'd ...


4
Kevin S Donnelly, Jun Kim, Bruno W Garlepp, Mark A Horowitz, Thomas H Lee, Pak Shing Chau, Jared L Zerbe, Clemenz L Portmann, Yiu Fai Chan: Circuitry for the delay adjustment of a clock signal. Rambus Incorporated, Pennie & Edmonds, August 31, 1999: US05945862 (65 worldwide citation)

Circuitry for adjusting the phase of an incoming periodic signal, typically a clock signal, throughout the entire period of the periodic signal. Phase adjustment circuitry has high resolution and employs only the number of delay elements in a delay chain necessary to span at least the period of the ...


5
Jared LeVan Zerbe, Michael Tak kei Ching, Abhijit M Abhyankar, Richard M Barth, Andy Peng Pui Chan, Paul G Davis, William F Stonecypher: Method and apparatus for fail-safe resynchronization with minimum latency. Rambus Incorporated, Pennie & Edmonds, October 29, 2002: US06473439 (65 worldwide citation)

A method and circuit for achieving minimum latency data transfer between two mesochronous (same frequency, different phase) clock domains is disclosed. This circuit supports arbitrary phase relationships between two clock domains and is tolerant of temperature and voltage shifts after initialization ...


6
Donald C Stark, Jun Kim, Kurt T Knorpp, Michael Tak Kei Ching, Natsuki Kushiyama: Impedance controlled output driver. Rambus Incorporated, Pennie & Edmonds, December 19, 2000: US06163178 (57 worldwide citation)

An output driver has an output multiplexor and an output current driver. The output multiplexor receives a data signal and outputs a q-node signal. The output current driver receives the q-node signal and drives a bus based on the q-node signal. The output multiplexor processes the data signal in va ...


7
Billy Wayne Garrett Jr, John B Dillon deceased, Michael Tak Kei Ching, William F Stonecypher, Andy Peng Pui Chan, Matthew M Griffin: Current control technique. Rambus Incorporated, Pennie & Edmonds, July 25, 2000: US06094075 (56 worldwide citation)

An output driver circuit and current control technique to facilitate high-speed buses with low noise is used to interface with high-speed dynamic RAMs (DRAMs). The architecture includes the following components: an input isolation block (120), an analog voltage divider (104), an input comparator (12 ...


8
Frederick A Ware, Kevin S Donnelly, Ely K Tsern, Srinivas Nimmagadda: Apparatus and method for generating a distributed clock signal using gear ratio techniques. Rambus Incorporated, Pennie & Edmonds, May 28, 2002: US06396887 (36 worldwide citation)

The present invention provides a method and apparatus for synchronizing signal transfers between two clock domains, where the clock domains have a gear ratio relationship. A gear ratio means that the clocks are related by a ratio, such that each clock has a different integer number of clock cycles i ...


9
Jared L Zerbe: Low-latency small-swing clocked receiver. Rambus Incorporated, William S Pennie & Edmonds Galliani, November 2, 1999: US05977798 (34 worldwide citation)

The present invention achieves the stated input receiver goals by merging many of the different functions required into a single unit instead of serializing them in the more traditional fashion. The present invention provides a receiver circuit having both a source-follower pair of MOS transistors, ...


10
Donald V Perino, Haw Jyh Liaw, Kevin S Donnelly: Apparatus and method for reducing clock signal phase skew in a master-slave system with multiple latent clock cycles. Rambus Incorporated, Pennie & Edmonds, July 30, 2002: US06426984 (33 worldwide citation)

A digital system includes a master device, a set of slave devices, and a clock generator to generate a clock signal. A transmission channel includes a clock-to-master path extending from the clock generator, through the set of slave devices, to the master device. The transmission channel also includ ...