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Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel, Metaram, KOTAB Dominic M, August 23, 2007: WO/2007/095080 (76 worldwide citation)

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints ...


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Rajan Suresh, Smith Michael, Wang David: Methods and apparatus of stacking drams. Metaram, Rajan Suresh, Smith Michael, Wang David, ZILKA Kevin J, March 8, 2007: WO/2007/028109 (71 worldwide citation)

Large capacity memory systems (FB-DIMMs) are constructed using stacked memory integrated circuits (220) or chips (310). The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


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Rajan Suresh N: An integrated memory core and memory interface circuit. Metaram, Rajan Suresh N, STATTLER John, January 4, 2007: WO/2007/002324 (19 worldwide citation)

A memory device comprises a first and second integrated circuit dies. The first integrated circuit die comprises a memory core as well as a first interface circuit. The first interface circuit permits full access to the memory cells (e.g., reading, writing, activating, pre-charging and refreshing op ...


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Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Metaram, Rajan Suresh Natarajan, Schakel Keith R, Smith Michael John Sebastian, Wang David T, Weber Frederick Daniel, ZILKA Kevin J, May 29, 2008: WO/2008/063251 (10 worldwide citation)

A memory circuit system (Figure 1) and method are provided in the context of various embodiments. In one embodiment, an interface circuit (102) remains in communication with a plurality of memory circuits (104) and a system. The interface circuit is operable to interface the memory circuits and the ...



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