1
David White, Taber H Smith: Characterization and verification for integrated circuit designs. Praesagus, Bingham McCutchen, February 6, 2007: US07174520 (252 worldwide citation)

Variations are characterized in feature dimensions of an integrated circuit that is to be fabricated in accordance with a design by a process that produces topographical variation in the integrated circuit, the variations in feature dimension being caused by the topographical variations. The process ...


2
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Bingham McCutchen, October 17, 2006: US07124386 (251 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


3
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus, Fish & Richardson P C, December 19, 2006: US07152215 (238 worldwide citation)

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...


4
David White, Taber H Smith: Test masks for lithographic and etch processes. Praesagus, Bingham McCutchen, July 10, 2007: US07243316 (187 worldwide citation)

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated ...


5
Smith Taber H, White David, Mehrotra Vikas: Characterization adn reduction of variation for integrated circuits. Praesagus, May 25, 2005: EP1532670-A2 (2 worldwide citation)

A method and system are described to reduce process variation as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation and electrical impact to modify the design and manufacture of integrated circuits.


6
Smith Taber H, White David, Mehrotra Vikas: Characterization adn reduction of variation for integrated circuits. Praesagus, Smith Taber H, White David, Mehrotra Vikas, FEIGENBAUM David L, December 18, 2003: WO/2003/104921 (2 worldwide citation)

A method and system are described to reduce process variation (10146) as a result of the semiconductor processing of films in integrated circuit manufacturing processes. The described methods use process variation (10146) and electrical impact (10154) to modify the design and manufacture of integrat ...


7
David White, Taber H Smith: Electronic design for integrated circuits based process related variations. Praesagus, Bingham McCutchen, April 3, 2007: US07200823

An electronic design is generated for an integrated circuit that is to be fabricated in accordance with the electronic design by a process that will impart topographically induced feature dimension variations to the integrated circuit. The generating includes adjusting the electronic design based on ...


8
David White, Taber H Smith: Adjustment of masks for integrated circuit fabrication. Praesagus, Fish & Richardson P C, May 2, 2006: US07039895

A pattern-dependent model is used to predict characteristics of an integrated circuit that is to be fabricated in accordance with a design by a process. The process includes (a) a fabrication process that will impart topographical variation to the integrated circuit and (b) a lithography or etch pro ...


9
David White, Taber H Smith: Test masks for lithographic and etch processes. Praesagus, Fish & Richardson P C, June 13, 2006: US07062730

A mask design is generated for patterning a test wafer using a lithographic or etch process, the process is characterized based on the patterned test wafer, and a pattern-dependent model is used based on the characterization to predict characteristics of integrated circuits that are to be fabricated ...


10
Taber H Smith, Vikas Mehrotra, David White: Dummy fill for integrated circuits. Praesagus a Massachusetts Corporation, Fish & Richardson PC, February 17, 2005: US20050037522-A1

A method and system are described to reduce process variation as a result of the electrochemical deposition (ECD), also referred to as electrochemical plating (ECP), and chemical mechanical polishing (CMP) processing of films in integrated circuit manufacturing processes. The described methods use p ...



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