1
Vikram Chopra, Ajay Desai, Raghunath Iyer, Sundar Iyer, Moti Jiandani, Ajit Shelat, Navneet Yadav: Method and apparatus for high-speed network rule processing. PMC Sierra US, Dag Johansen, Stattler Johansen & Adeli, January 21, 2003: US06510509 (95 worldwide citation)

A high-speed rule processing apparatus is disclosed that may be used to implement a wide variety of rule processing tasks such as network address translation, firewall protection, quality of service, IP routing, and/or load balancing. The high-speed rule processor uses an array of compare engines th ...


2
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with error detection for concatenated error correction codes. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, December 31, 2013: US08621318 (49 worldwide citation)

A nonvolatile memory controller to recover encoded data by performing a hard-decision inner error correction code decoding and an outer error correction code decoding of the data decoded using the hard-decision inner error correction code decoding and then determining if the encoded data has been su ...


3
Babysaroja Annem, Heng Liao, Zhongzhi Liu, Praveen Alexander: Logical address direct memory access with multiple concurrent physical ports and internal switching. PMC Sierra US, Dennis R Haszko, January 25, 2011: US07877524 (48 worldwide citation)

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function ...


4
Babysaroja Annem, David J Clinton, Praveen Alexander: Logical address direct memory access with multiple concurrent physical ports and internal switching. PMC Sierra US, Dennis R Haszko, September 18, 2012: US08271700 (39 worldwide citation)

A DMA engine is provided that is suitable for higher performance System On a Chip (SOC) devices that have multiple concurrent on-chip/off-chip memory spaces. The DMA engine operates either on logical addressing method or physical addressing method and provides random and sequential mapping function ...


5
Rino Micheloni, Alessia Marelli, Peter Z Onufryk, Christopher I W Norrie: Nonvolatile memory controller with concatenated error correction codes. PMC Sierra US, Kenneth Glass, Molly Sauter, Glass & Associates, February 18, 2014: US08656257 (28 worldwide citation)

A nonvolatile memory controller may recover encoded data using the outer error correction code of the encoded data if it is determined that a correction capacity of the outer error correction code is not exceeded. Alternatively, the nonvolatile memory controller may recover the encoded data using th ...


6
Rino Micheloni, Luca Crippa, Alessia Marelli: Error correction code technique for improving read stress endurance. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694855 (27 worldwide citation)

A data storage device reads a data unit from a memory page, detects a number of data bit errors in the data unit, and generates a bit error indicator identifying bit indexes of the data bit errors in the data unit. The data storage device reads the data unit from the memory page once again and gener ...


7
Rino Micheloni, Alessia Marelli, Peter Z Onufryk: Shuffler error correction code system and method. PMC Sierra US, Kenneth Glass, Stanley J Pawlik, Glass & Associates, April 8, 2014: US08694849 (25 worldwide citation)

A data storage device stores a data unit in a memory page of a storage block along with an error correction code unit for the data unit. Additionally, the data storage device stores an error correction code unit for the data unit in a memory page of another storage block. In various embodiments, one ...


8
Raymond Lam, Cheng Yi: System and method for multiengine operation with super descriptor in SAS/SATA controller wherein portion of super-descriptor is executed without intervention of initiator. PMC Sierra US, Dennis R Haszko, June 24, 2014: US08762609 (25 worldwide citation)

A method of chaining a plurality of engines for a system on chip (SOC) controller device and a SOC controller device are disclosed herein. The method comprises: generating, at an initiator, a super-descriptor for providing instructions to the plurality of engines of the SOC controller; passing the s ...


9
Alan Coady, Zixiong Wang: Delay measurements and calibration methods and apparatus for distributed wireless systems. PMC Sierra US, Curtis B Behmann, Borden Ladner Gervais, May 10, 2011: US07940667 (24 worldwide citation)

Delay measurement and delay calibration methods and apparatus are described for use within distributed wireless base stations employing a remote radio head topology. The methods and apparatus are usable in any system that requires accurate delay measurement and/or constant delay through an electroni ...


10
Christopher I W Norrie: System and method for avoiding error mechanisms in layered iterative decoding. PMC Sierra US, Kenneth Glass, Molly Sauter, Glass & Associates, March 17, 2015: US08984376 (23 worldwide citation)

A low-density parity check (LDPC) decoder is provided for decoding low-density parity check (LDPC) encoded data wherein the processing order of the layers of the LDPC parity check matrix are rearranged during the decode process in an attempt to avoid error mechanisms brought about by the iterative n ...