1
Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T: System and method for handling exceptional instructions in a trace cache based processor. Advanced Micro Devices, Alsup Mitchell, Smaus Gregory William, Pickett James K, Mccinn Brian D, Filippo Michael A, Sander Benjamin T, DRAKE Paul S, May 6, 2005: WO/2005/041024 (4 worldwide citation)

A system may include an instruction cache (106), a trace cache (160) including a plurality of trace cache entries (162), and a trace generator (170) coupled to the instruction cache (106) and the trace cache (160). The trace generator (170) may be configured to receive a group of instructions output ...


2
Filippo Michael A, Pickett James K: Processor with dependence mechanism to predict whether a load is dependent on older store. Advanced Micro Devices, Filippo Michael A, Pickett James K, sDRAKE Paul S, March 16, 2006: WO/2006/028555 (4 worldwide citation)

A processor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler. The load store unit (126C) is configured to store information identifying memory operations issued to the load store unit (126C ...


3
Filippo Michael A, Pickett James K, Sander Benjamin T, Gopal Rama S: Load store unit with replay mechanism. Advanced Micro Devices, Filippo Michael A, Pickett James K, Sander Benjamin T, Gopal Rama S, DRAKE Paul S, December 23, 2004: WO/2004/111839

A microprocessor (100) may include a scheduler (118) configured to issue operations and a load store unit (126C) configured to execute memory operations issued by the scheduler (118). The load store unit (126C) is configured to store information identifying memory operations issued to the load store ...


4
Filippo Michael A, Pickett James K: Store-to-load forwarding buffer using indexed lookup. Advanced Micro Devices, Filippo Michael A, Pickett James K, DRAKE Paul S, February 3, 2005: WO/2005/010750

A microprocessor (100) may include a dispatch unit (104) configured to dispatch load and store operations and a load store unit (126) configured to store information associated with load and store operations dispatched by the dispatch unit (104). The load store unit (126) includes a STLF (Store-to-L ...


5
Filippo Michael A, Pickett James K, Sander Benjamin T: System and method for operation replay within a data-speculative microprocessor. Advanced Micro Devices, Filippo Michael A, Pickett James K, Sander Benjamin T, sDRAKE Paul S, November 18, 2004: WO/2004/099977

A microprocessor (100) may include one or more functional units (126) configured to execute operations, a scheduler (118) configured to issue operations to the functional units (126) for execution, and at least one replay detection unit. The scheduler (118) may be configured to maintain state inform ...


6
Filippo Michael A, Pickett James K, Sander Benjamin T: Apparatus and method to identify data-speculative operations in microprocessor. Advanced Micro Devices, Filippo Michael A, Pickett James K, Sander Benjamin T, sDRAKE Paul S, November 18, 2004: WO/2004/099978

A microprocessor (100) may include a retire queue (102) and one or more data speculation verification units. The data speculation verification units are each configured to verify data speculation performed on operations. Each data speculation verification unit generates a respective speculation poin ...


7
Pickett James K, Sander Benjamin Thomas, Lepak Kevin Michael: Data speculation based on addressing patterns identifying dual-purpose register. Advanced Micro Devices, Pickett James K, Sander Benjamin Thomas, Lepak Kevin Michael, DRAKE Paul S, August 12, 2004: WO/2004/068341

A system may include a memory file (136) and an execution core (124). The memory file (136) may include an entry (420) configured to store an addressing pattern (406) and a tag (408). If an addressing pattern of a memory operation matches the addressing pattern (406) stored in the entry (420), the m ...