1
Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven: Diode array architecture for addressing nanoscale resistive memory arrays. Spansion, Tripsas Nicholas H, Bill Colin S, Vanbuskirk Michael A, Buynoski Matthew, Fang Tzu Ning, Cai Wei Daisy, Pangrle Suzette K, Avanzino Steven, LAM Christine S, May 26, 2006: WO/2006/055482 (12 worldwide citation)

The present memory structure includes thereof a first conductor (BL), a second conductor (WL), a resistive memory cell (130) connected to the second conductor (WL), a first diode (134) connected to the resistive memory cell (130) and the first conductor (BL), and oriented in the forward direction fr ...


2
Buynoski Matthew S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H: Self assembly of conducting polymer for formation of polymer memory cell. Advanced Micro Devices, Buynoski Matthew, S, Pangrle Suzette K, Okoroanyanwu Uzodinma, Tripsas Nicholas H, sDRAKE Paul S, May 6, 2005: WO/2005/041319 (1 worldwide citation)

The present invention provides a selectively conductive organic semiconductor (e.g., polymer) device that can be utilized as a memory cell. A polymer solution including a conducting polymer (22) self assembles relative to a conductive electrode (26). The process affords self-assembly such that a sho ...


3
Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V: Polymer memory device formed in via opening. Advanced Micro Devices, Tripsas Nicholas H, Buynoski Matthew, Pangrle Suzette K, Okoroanyanwu Uzodinma, Hui Angela T, Lyons Christopher F, Subramanian Ramkumar, Lopatin Sergey D, Ngo Minh Van, Khathuria Ashok M, Chang Mark S, Cheung Patrick K, Oglesby Jane V, sCOLLOPY Daniel R, February 3, 2005: WO/2005/010892

One aspect of the present invention relates to a method of fabricating a polymer memory device in a via. The method involves providing a semiconductor substrate having at least one metal-containing layer thereon, forming at least one copper contact in the metal-containing layer, forming at least one ...


4
Sokolik Igor, Kingborough Richard P, Leonard William G, Yudanov Nicolay F, Pangrle Suzette K, Tripsas Nicholas H, Ngo Minh Van: System and method for processing an organic memory cell. Spansion, Advanced Micro Devices, Sokolik Igor, Kingborough Richard P, Leonard William G, Yudanov Nicolay F, Pangrle Suzette K, Tripsas Nicholas H, Ngo Minh Van, JAIPERSHAD Rajendra, May 3, 2007: WO/2007/050270

A system (200) and method are disclosed for processing an organic memory cell. An exemplary system (200) can employ an enclosed processing chamber (202), a passive layer formation component (204) operative to form a passive layer on a first electrode, and an organic semiconductor layer formation com ...


5
Pangrle Suzette K, Sokolik Igor, Krieger Juri: Stackable memory device and organic transistor structure. Spansion, Pangrle Suzette K, Sokolik Igor, Krieger Juri, JAIPERSHAD Rajendra, January 11, 2007: WO/2007/005871

In the present electronic structure (60), a first electronic device (74) includes a first pair of electrodes (76, 82) and an active layer (80) between the first pair of electrodes (76, 82). An organic transistor (100) is made up of organic material (88), a source (90), a drain (92), and a gate (96), ...


6
Sokolik Igor, Kingsborough Richard, Gaun David, Kaza Swaroop, Spitzer Stuart, Pangrle Suzette K: Resitive memory device with improved data retention. Spansion, Sokolik Igor, Kingsborough Richard, Gaun David, Kaza Swaroop, Spitzer Stuart, Pangrle Suzette K, JAIPERSHAD Rajendra, January 11, 2007: WO/2007/005872

The present memory device (130) includes first and second electrodes (132, 138), a passive layer (134) between the first and second electrodes (132, 138) and an active layer (136) between the first and second electrodes (132, 138), the active layer (136) being of a material containing randomly orien ...


7
BARRIE Keith Lake, PANGRLE Suzette K, VILLAVICECIO Grant, LEAL Jeffrey S: MATRICE EN SEMICONDUCTEUR MUNIE DINTERCONNEXIONS ÉLECTRIQUES À PAS FIN, SEMICONDUCTOR DIE HAVING FINE PITCH ELECTRICAL INTERCONNECTS. VERTICAL CIRCUITS, BARRIE Keith Lake, PANGRLE Suzette K, VILLAVICECIO Grant, LEAL Jeffrey S, KENNEDY Bill, April 19, 2012: WO/2012/050812

A die has interconnect pads on an interconnect side near an interconnect edge and has at least a portion of the interconnect side covered by a conformal dielectric coating, in which an interconnect trace over the dielectric coating forms a high interface angle with the surface of the dielectric coat ...


8
CO Reynaldo, LEAL Jeffrey S, PANGRLE Suzette K, MCGRATH Scott, MELCHER DeAnn Eileen, BARRIE Keith L, VILLLAVICENCIO Grant, DEL ROSARIO Elmer M, BRAY John R: Connecteur électrique entre pastille de puce et interconnexion z pour ensembles de puces empilées, Electrical connector between die pad and z-interconnect for stacked die assemblies. Vertical Circuits, CO Reynaldo, LEAL Jeffrey S, PANGRLE Suzette K, MCGRATH Scott, MELCHER DeAnn Eileen, BARRIE Keith L, VILLLAVICENCIO Grant, DEL ROSARIO Elmer M, BRAY John R, KENNEDY Bill, November 24, 2011: WO/2011/146579

Methods for forming connectors on die pads at a wafer level of processing include forming spots of a curable electrically conductive material over die pads and extending to or over the interconnect die edge; curing the conductive material; and in a wafer cutting procedure thereafter severing the spo ...


9
Pangrle Suzette K, Avanzino Steven, Haddad Sameer, Vanbuskirk Michael, Rathor Manuj, Xie James, Song Kevin, Marrian Christie, Choo Bryan, Wang Fei, Shields Jeffrey A: (mim) Device with improved scaleability. Advanced Micro Devices, Spansion, Pangrle Suzette K, Avanzino Steven, Haddad Sameer, Vanbuskirk Michael, Rathor Manuj, Xie James, Song Kevin, Marrian Christie, Choo Bryan, Wang Fei, Shields Jeffrey A, sDRAKE Paul S, March 20, 2008: WO/2008/033332

A present method of fabricating a memory device includes the steps of providing a dielectric layer (110), providing an opening (1 12) in the dielectric layer (110), providing a first conductive body ( 116A) in the opening (112), providing a switching body ( 118A) in the opening (112), the first cond ...


10
Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A: Protection of active layers of memory cells during processing of other elements. Spansion, Avanzino Steven, Sokolik Igor, Pangrle Suzette K, Tripsas Nicholas H, Shields Jeffrey A, LAM Christine S, May 18, 2006: WO/2006/053163

A method of fabricating an electronic structure by providing a conductive layer (102), providing a dielectric layer (100) over the conductive layer (102), providing first and second openings (104, 106) through the dielectric layer (100), providing first and second conductive bodies (108, 110) in the ...



Click the thumbnails below to visualize the patent trend.