1
Martin Vorbach, Robert Münch: Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. PACT XPP Technologies, Kenyon & Kenyon, March 7, 2006: US07010667 (179 worldwide citation)

An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus ...


2
Martin Vorbach, Robert Münch: Method of repairing integrated circuits. Pact XPP Technologies, Kenyon & Kenyon, February 24, 2004: US06697979 (119 worldwide citation)

An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (e.g., arithmetic and logic units), with a function unit. The arrangement and the method provide for performing self-tests more easily, less expensively and before or during a running of a ...


3
Martin Vorbach, Robert Münch: Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.). PACT XPP Technologies, Kenyon & Kenyon, May 27, 2003: US06571381 (91 worldwide citation)

A method of deadlock-free, automatic configuration and reconfiguration of modules having a two- or multidimensional cell arrangement, in which a unit for controlling the configuration and reconfiguration manages a set of associated configurable elements, the set being a subset or the total set of al ...


4
Frank May, Armin Nückel, Martin Vorbach: Method for translating programs for reconfigurable architectures. PACT XPP Technologies, Kenyon & Kenyon, April 24, 2007: US07210129 (80 worldwide citation)

A method for translating high-level languages to reconfigurable architectures is disclosed. The method includes building a finite automaton for calculation. The method further includes forming a combinational network of a plurality of individual functions in accordance with the structure of the fini ...


5
Martin Vorbach, Robert Münch: Method of hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs , etc.). Pact XPP Technologies, Kenyon & Kenyon, February 3, 2004: US06687788 (79 worldwide citation)

A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a gro ...


6
Martin Vorbach, Robert Münch: I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures. PACT XPP Technologies, Kenyon & Kenyon, April 13, 2004: US06721830 (65 worldwide citation)

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (fo ...


7
Martin Vorbach, Robert Münch: Runtime configurable arithmetic and logic cell. PACT XPP Technologies, Kenyon & Kenyon, April 27, 2004: US06728871 (61 worldwide citation)

A cascadable arithmetic and logic unit (ALU) which is configurable in function and interconnection. No decoding of commands is needed during execution of the algorithm. The ALU can be reconfigured at run time without any effect on surrounding ALUs, processing units or data streams. The volume of con ...


8
Martin Vorbach, Robert Münch: Reconfigurable multidimensional array processor allowing runtime reconfiguration of selected individual array cells. Pact XPP Technologies, Kenyon & Kenyon, June 26, 2007: US07237087 (58 worldwide citation)

An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded fre ...


9
Martin Vorbach, Robert Münch: Process for automatic dynamic reloading of data flow processors (DFPS) and units with two- or three- dimensional programmable cell architectures (FPGAS, DPGAS, and the like). Pact XPP Technologies, Kenyon & Kenyon, April 11, 2006: US07028107 (52 worldwide citation)

A system for communication between a plurality of functional elements in a cell arrangement and a higher-level unit is described. The system may include, for example, a configuration memory arranged between the functional elements and the higher-level unit; and a control unit configured to move at l ...


10
Vorbach Martin, Muench Robert: Method for self-synchronization of configurable elements of a programmable component. Pact Xpp Technologies, June 14, 2006: EP1669885-A2 (50 worldwide citation)

A data processing system has a number of programmable modules that allow reconfiguration to be made and can be organised in two or three dimensional form. The modules are operated in a synchronised mode using signals that are generated with the data stream transmitted between the modules. The synchr ...