1
Martin Vorbach, Robert Münch: Internal bus system for DFPS and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. PACT XPP Technologies, Kenyon & Kenyon, March 7, 2006: US07010667 (179 worldwide citation)

An internal bus system for DFPs and units with two- or multi-dimensional programmable cell architectures, for managing large volumes of data with a high interconnection complexity. The bus system can transmit data between a plurality of function blocks, where multiple data packets can be on the bus ...


2
Martin Vorbach, Robert Münch: Process for automatic dynamic reloading of data flow processors (dfps) and units with two-or-three-dimensional programmable cell architectures (fpgas, dpgas, and the like). PACT, Kenyon & Kenyon, November 5, 2002: US06477643 (153 worldwide citation)

A method for processing data in a configurable unit having a multidimensional cell arrangement a switching table is provided, the switching table including a controller and a configuration memory. Configuration strings are transmitted from the switching table to a configurable element of the unit to ...


3
Martin Vorbach, Robert Münch: Method of repairing integrated circuits. Pact XPP Technologies, Kenyon & Kenyon, February 24, 2004: US06697979 (119 worldwide citation)

An arrangement and a method are provided for replacing defective units, which can be any desired unit of a chip (e.g., arithmetic and logic units), with a function unit. The arrangement and the method provide for performing self-tests more easily, less expensively and before or during a running of a ...


4
Martin Vorbach, Robert Münch: Method for hierarchical caching of configuration data having dataflow processors and modules having two-or multidimensional programmable cell structure (FPGAs, DPGAs, etc.)--. PACT Informationstechnologie, Kenyon & Kenyon, November 12, 2002: US06480937 (114 worldwide citation)

A method of caching commands in microprocessors having a plurality of arithmetic units and in modules having a two- or multidimensional cell arrangement is provided. The method includes combining a plurality of cells and arithmetic units to form a plurality of groups, assigning a cache unit to a gro ...


5
Martin Andreas Vorbach, Robert Markus Munch: Dynamically reconfigurable data processing system. PACT, Kenyon & Kenyon, August 24, 1999: US05943242 (102 worldwide citation)

A data processing system, wherein a data flow processor (DFP) integrated circuit chip is provided which comprises a plurality of orthogonally arranged homogeneously structured cells, each cell having a plurality of logically same and structurally identically arranged modules. The cells are combined ...


6
Martin Vorbach, Robert Münch: UNIT FOR PROCESSING NUMERIC AND LOGIC OPERATIONS FOR USE IN CENTRAL PROCESSING UNITS (CPUS), MULTIPROCESSOR SYSTEMS, DATA-FLOW PROCESSORS (DSPS), SYSTOLIC PROCESSORS AND FIELD PROGRAMMABLE GATE ARRAYS (EPGAS). PACT, Kenyon & Kenyon, July 23, 2002: US06425068 (101 worldwide citation)

An expanded arithmetic and logic unit (EALU) with special extra functions is integrated into a configurable unit for performing data processing operations. The EALU is configured by a function register, which greatly reduces the volume of data required for configuration. The cell can be cascaded fre ...


7
Martin Vorbach, Robert Munch: I/O and memory bus system for DFPs and units with two- or multi-dimensional programmable cell architectures. PACT, Kenyon & Kenyon, September 12, 2000: US06119181 (99 worldwide citation)

A uniform bus system is provided which operates without any special consideration by a programmer. Memories and peripheral may be connected to this bus system without any special measures. Likewise, units may be cascaded with the help of the bus system. The bus system combines a number of internal l ...


8
Martin Vorbach, Robert Munch: Run-time reconfiguration method for programmable units. PACT, Kenyon & Kenyon, February 1, 2000: US06021490 (98 worldwide citation)

A method of run-time reconfiguration of a programmable unit is provided, the programmable unit including a plurality of reconfigurable function cells in a multidimensional arrangement. An event is detected. The source of the detected event is determined, and an address of an entry in a jump table is ...


9
Martin Vorbach, Robert Münch: I/O and memory bus system for DFPS and units with two or multi-dimensional programmable cell architectures. PACT, Kenyon & Kenyon, January 8, 2002: US06338106 (95 worldwide citation)

A general bus system is provided which combines a number of internal lines and leads them as a bundle to the terminals. The bus system control is predefined and does not require any influence by the programmer. Any number of memories, peripherals or other units can be connected to the bus system (fo ...


10
Martin Vorbach, Robert Münch: Method for deadlock-free configuration of dataflow processors and modules with a two- or multidimensional programmable cell structure (FPGAs, DPGAs, etc.). PACT XPP Technologies, Kenyon & Kenyon, May 27, 2003: US06571381 (91 worldwide citation)

A method of deadlock-free, automatic configuration and reconfiguration of modules having a two- or multidimensional cell arrangement, in which a unit for controlling the configuration and reconfiguration manages a set of associated configurable elements, the set being a subset or the total set of al ...