1
Charles E Ellenberger, George L Bower, William R Snow: Independently variably controlled pulsed R.F. plasma chemical vapor processing. Pacific Western Systems, Harry E Aine, February 19, 1985: US04500563 (193 worldwide citation)

Semiconductive wafers are processed, i.e., etched or layers deposited thereon, by means of a plasma enhanced chemical vapor processing system wherein the plasma is generated by a train of R.F. power pulses. The pulse repetition rate, pulse length and peak power level of the individual pulses are ind ...


2
George M Engle Jr: Plasma enhanced chemical vapor processing of semiconductive wafers. Pacific Western Systems, Harry E Aine, Harvey G Lowhurst, September 16, 1980: US04223048 (83 worldwide citation)

Semiconductive wafers are processed, i.e., etched or layers deposited thereon, by means of a plasma enhanced chemical vapor processing system. The processing system includes an evacuable horizontal tubular envelope disposed within a surrounding heater or furnace for maintaining, the case of depositi ...


3
John D Schmidt: Memory tester having concurrent failure data readout and memory repair analysis. Pacific Western Systems, Harry E Aine, April 5, 1988: US04736373 (52 worldwide citation)

A memory tester for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and columns in a se ...


4
Keith A Frost, Timothy Harns, Ronald D Simmons: Interface system for interfacing a device tester to a device under test. Pacific Western Systems, Harry E Aine, January 3, 1989: US04795977 (46 worldwide citation)

A device tester, such as a memory tester, is electrically interfaced to a device under test, such as a memory die, by means of an improved interface system. The interface system includes an array of coaxial cables for making electrical connection to the test circuits of the device tester by means of ...


5
Daniel A Worsham, Jack E Ashley, Joseph M Munoz: Probe head for an automatic semiconductive wafer prober. Pacific Western Systems, Harry E Aine, Harvey G Lowhurst, February 17, 1981: US04251772 (46 worldwide citation)

In a probe head for an automatic semiconductive wafer prober, the probe head includes a probe body means for coupling the probe head to the probe holder surrounding a chuck which carries the wafer. The chuck is moveable in the plane of the wafer (horizontal) and orthogonal to the plane of the wafer ...


6
Jerry W Zimmer, Daniel A Worsham: Diamond probe tip. Pacific Western Systems, SP3, Thomas Schneck, John P McGuire Jr, June 9, 1998: US05763879 (45 worldwide citation)

A probe for electrical contact with a metal layer of an integrated circuit wherein the probe features a polycrystalline diamond layer coating a fine conductive wire. The diamond coating has exposed pyramidal facets having a density of at least 2000 per square millimeter. The substrate has a radius e ...


7
John D Schmidt: Memory tester having memory repair analysis under pattern generator control. Pacific Western Systems, Harry E Aine, July 17, 1984: US04460999 (44 worldwide citation)

A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix under address control of a programmable pattern generator to derive failure dat ...


8
Vernon C Milligan: Automatic wafer prober having a probe scrub routine. Pacific Western Systems, Harry E Aine, May 20, 1986: US04590422 (43 worldwide citation)

In an automatic wafer prober, the prober steps through a certain predetermined sequence of die on the wafer. After a certain predetermined number of die have been probed, the prober automatically interrupts the probing sequence and steps the prober off of the wafer onto an abrasive element for scrub ...


9
Timothy Harns: Memory tester having memory repair analysis capability. Pacific Western Systems, Harry E Aine, July 17, 1984: US04460997 (33 worldwide citation)

A memory tester is disclosed for testing a matrix of memory elements, such matrix having spare rows and columns of memory elements to be used for repair of the memory under test. The memory tester tests the memory matrix to derive failure data and stores the failure data in corresponding rows and co ...


10
Wayne R Merryman: Timing pulse generator. Pacific Western Systems, Harry E Aine, Harvey G Lowhurst, July 18, 1978: US04101761 (22 worldwide citation)

A timing pulse generator for testing electronic components such as semiconductor memories, which tests require time accuracy and repeatability.