1
Luc R Bisson, Oren Rubinstein, Wei Je Huang, Michael B Diamond: Apparatus, system, and method for bus link width optimization. NVIDIA Corporation, Cooley Godward, November 14, 2006: US07136953 (145 worldwide citation)

A bus permits the number of active serial data lanes of a data link to be re-negotiated in response to changes in bus bandwidth requirements. In one embodiment, one of the bus interfaces triggers a re-negotiation of link width and places a constraint on link width during the re-negotiation.


2
Ming B Zhu: Rendering pipeline. NVIDIA Corporation, Townsend and Townsend and Crew, January 30, 2007: US07170515 (141 worldwide citation)

A rendering pipeline system for a computer environment uses screen space tiling (SST) to eliminate the memory bandwidth bottleneck due to frame buffer access and performs screen space tiling efficiently, while avoiding the breaking up of primitives. The system also reduces the buffering size require ...


3
John Shigeto Minami, Robin Yasu Uyeshiro, Michael Ward Johnson, Steve Su, Michael John Sebastian Smith, Addison Kwuanming Chen, Mihir Shaileshbhai Doctor, Daniel Leo Greenfield: Gigabit ethernet adapter supporting the iSCSI and IPSEC protocols. NVIDIA Corporation, Zilka Kotab PC, May 19, 2009: US07535913 (132 worldwide citation)

The invention is embodied in a gigabit Ethernet adapter. A system according to the invention provides a compact hardware solution to handling high network communication speeds. In addition, the invention adapts to multiple communication protocols via a modular construction and design.


4
Jonah Alben, Dennis Kd Ma, Brian Kelleher: Method and apparatus for power management of graphics processors and subsystems that allow the subsystems to respond to accesses when subsystems are idle. NVIDIA Corporation, Moser Patterson & Sheridan, August 30, 2005: US06938176 (126 worldwide citation)

A graphics processing device implementing a set of techniques for power management, preferably at both a subsystem level and a device level, and preferably including peak power management, a system including a graphics processing device that implements such a set of techniques for power management, ...


5
Franck R Diard, Rick M Iwamoto: Private addressing in a multi-processor graphics processing system. NVIDIA Corporation, Townsend and Townsend and Crew, October 18, 2005: US06956579 (112 worldwide citation)

Systems and methods for private addressing in a multi-processor graphics processing subsystem having a number of memories and a number of graphics processors. Each of the memories includes a number of addressable storage locations, and storage locations in different memories may share a common globa ...


6
Edward C Greene, Douglas A Voorhies, Paolo Sabella, John M Danskin, James M Van Dyke: Modified method and apparatus for improved occlusion culling in graphics systems. NVIDIA Corporation, Kevin J Zilka, Silicon Valley IP Group PC, November 11, 2003: US06646639 (111 worldwide citation)

A system, method and computer program product are provided for avoiding reading z-values in a graphics pipeline. Initially, near z-values are stored which are each representative of a near z-value on an object in a region. Such region is defined by a tile and a coverage mask therein. Thereafter, the ...


7
James M Van Dyke, John H Edmondson: Memory addressing controlled by PTE fields. NVIDIA Corporation, Patterson & Sheridan, September 28, 2010: US07805587 (110 worldwide citation)

Embodiments of the present invention enable virtual-to-physical memory address translation using optimized bank and partition interleave patterns to improve memory bandwidth by distributing data accesses over multiple banks and multiple partitions. Each virtual page has a corresponding page table en ...


8
Franck R Diard: Adaptive load balancing in a multi-processor graphics processing system. NVIDIA Corporation, Townsend and Townsend and Crew, July 11, 2006: US07075541 (108 worldwide citation)

Systems and methods for balancing a load among multiple graphics processors that render different portions of a frame. A display area is partitioned into portions for each of two (or more) graphics processors. The graphics processors render their respective portions of a frame and return feedback da ...


9
Ian A Buck, John R Nickolls, Michael C Shebanow, Lars S Nyland: Atomic memory operators in a parallel processor. NVIDIA Corporation, Townsend and Townsend and Crew, December 1, 2009: US07627723 (105 worldwide citation)

Methods, apparatuses, and systems are presented for updating data in memory while executing multiple threads of instructions, involving receiving a single instruction from one of a plurality of concurrently executing threads of instructions, in response to the single instruction received, reading da ...


10
Roger L Allen, Harold Robert Feldman Zatz: Method and apparatus for loop and branch instructions in a programmable graphics pipeline. NVIDIA Corporation, Moser Patterson & Sheridan, November 30, 2004: US06825843 (98 worldwide citation)

A method and apparatus for executing loop and branch program instructions in a programmable graphics shader. The programmable graphics shader converts a sequence of instructions comprising a portion of a shader program and selects a first set of fragments to be processed. Subsequent sequences of ins ...