1
Dimitrios Dimitrelis: Content addressable memory (CAM) device including match line sensing. NetLogic Microsystems, Shemwell Mahamedi, July 18, 2006: US07079407 (116 worldwide citation)

A content addressable memory (CAM) device that includes a plurality of CAM cells coupled to a match line to affect a voltage of the match line in response to data values of the CAM cells and comparand data being in a predetermined logical relationship, and a match detect circuit coupled to the match ...


2
Varadarajan Srinivasan, Bindiganavale S Nataraj, Sandeep Khanna: Method and apparatus for cascading content addressable memory devices. NetLogic Microsystems, Blakely Sokoloff Taylor & Zafman, November 14, 2000: US06148364 (115 worldwide citation)

A method and apparatus for cascading content addressable memory (CAM) devices is disclosed. The method and apparatus may be particularly useful when depth cascading CAM devices that operate in a flow-through mode. In the flow-through mode, a compare instruction may be simultaneously provided to each ...


3
Jose Pio Pereira, Varadarajan Srinivasan: Hierarchical depth cascading of content addressable memory devices. NetLogic Microsystems, William L Paradice III, November 13, 2001: US06317350 (114 worldwide citation)

A method and apparatus hierarchically cascades a number of memory devices to achieve a balance between the number of match flag inputs and the time required to generate the system match flag. In some embodiments, the number of match inputs required for each cascaded device and the time required to g ...


4
Michael E Ichiriu: Error-correcting content addressable memory. NetLogic Microsystems, Shemwell Gregory & Courtney, December 20, 2005: US06978343 (112 worldwide citation)

A content addressable memory (CAM) device having an error correction function. The CAM device includes an array of CAM cells, row parity storage elements and column parity storage elements. The row parity storage elements store row parity values that correspond to contents of respective rows of the ...


5
Dimitri Argyres: Fast quaternary content addressable memory cell. Netlogic Microsystems, Sterne Kessler Goldstein & Fox P L L C, June 11, 2013: US08462532 (107 worldwide citation)

Quaternary CAM cells are provided that include one or more compare circuits that each has a minimal number of pull-down transistors coupled between the match line and ground potential. For some embodiments, the compare circuit includes two parallel paths between the match line and ground potential, ...


6
Bartosz Banachowicz, Andrew Wright: Interlocking memory/logic cell layout and method of manufacture. Netlogic Microsystems, Bradley T Sako, October 24, 2006: US07126837 (105 worldwide citation)

A memory/logic cell layout structure includes a pair of memory/logic cells formed on a substrate. Each memory/logic cell (102, 104) can include a pair of memory areas to store data (106-0/106-1, 106-2/106-3), and a logic portion (108-0, 108-1) that receives the data stored therein. Memory areas and ...


7
Srinivasan Venkatachary: Memory optimized pattern searching. NetLogic Microsystems, Shemwell Mahamedi, William L Paradice III, July 21, 2009: US07565380 (100 worldwide citation)

A method of modifying a finite state machine (FSM) wherein the FSM is accessed by a plurality of entries, with each entry comprised of a substring and a next-state pointer, and the FSM is modified so that each entry comprises a length, which is less than or equal to a maximum size boundary placed on ...


8
Bindiganavale S Nataraj, Sandeep Khanna, Varadarajan Srinivasan: Ternary content addressable memory cell. NetLogic Microsystems, Blakely Sokoloff Taylor & Zafman, November 28, 2000: US06154384 (95 worldwide citation)

A ternary content addressable memory (CAM) cell. For one embodiment, the ternary CAM cell includes a first memory cell, a compare circuit, a second memory cell and a mask circuit. The first memory cell is coupled to a first pair of bit lines that carries data to and from the first memory cell. The c ...


9
Varadarajan Srinivasan, Sandeep Khanna, Bindiganavale S Nataraj: Method and apparatus for simultaneously performing a plurality of compare operations in content addressable memory device. NetLogic Microsystems, Blakely Sokoloff Taylor & Zafman, October 24, 2000: US06137707 (89 worldwide citation)

A method and apparatus for simultaneously performing a plurality compare operations in a content addressable memory (CAM) device. For one embodiment, the CAM device includes a CAM array having a plurality of CAM cells, a first comparand register for storing first comparand data, and a second compara ...


10
Varadarajan Srinivasan, Bindiganavale S Nataraj, Sandeep Khanna: Method for longest prefix matching in a content addressable memory. NetLogic Microsystems, William L Paradice III, May 22, 2001: US06237061 (89 worldwide citation)

A ternary content addressable memory is employed to perform a longest prefix match search. Each CAM cell within the ternary CAM has an associated mask cell so that the CAM cells may be individually masked so as to effectively store either a logic 0, a logic 1, or a don't care for compare operat ...