1
Craig C Hansen, Thomas J Riordan: RISC computer with unaligned reference handling and method for the same. Mips Computer Systems, Kenyon & Kenyon, March 21, 1989: US04814976 (114 worldwide citation)

In a RISC device a set of four instructions are provided which allow either the loading or the storage of an unaligned reference. The instructions are overlapped to reduce the overall execution time of the device. A circuit is also provided for executing the instruction set.


2
George S Taylor, P Michael Farmwald, Timothy P Layman, Huy X Ngo, Allen W Roberts: Two-level cache memory system. Mips Computer Systems, Townsend and Townsend Khourie and Crew, April 26, 1994: US05307477 (89 worldwide citation)

A two-level cache memory system for use in a computer system including two primary cache memories, one for storing instructions and one for storing data. The system also includes a secondary cache memory for storing both instructions and data. The primary and secondary caches each employ their own s ...


3
John P Moussouris, Lester M Crudele, Steven A Przybylski: Cup chip having tag comparator and address translation unit on chip and connected to off-chip cache and main memories. MIPS Computer Systems, Kenyon & Kenyon, August 28, 1990: US04953073 (84 worldwide citation)

A cache-based computer architecture has the address generating unit and the tag comparator packaged together and separately from the cache RAMS. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, the address generating ...


4
Larry B Weber, Craig C Hansen, Thomas J Riordan, Steven A Przybylski: Dual byte order computer architecture a functional unit for handling data sets with differnt byte orders. Mips Computer Systems, Kenyon & Kenyon, September 25, 1990: US04959779 (81 worldwide citation)

A CPU or other function unit is disclosed which follows one data ordering scheme internally, and in which incoming and/or outgoing data pass through a data order conversion unit for adapting it to a selectable external data ordering scheme. The means for specifying the external data ordering scheme ...


5
Paul M Farmwald, Timothy S C Fu: Slot determination mechanism using pulse counting. MIPS Computer Systems, Townsend and Townsend, January 12, 1993: US05179670 (67 worldwide citation)

A slot determination mechanism wherein a number of bus units establish their positions along the bus and the total number of units on the bus. The units are connected in a bidirectional daisy chain. A one-cycle reset pulse is sent downstream to unit 1 (the upstream unit). Each unit on receiving one ...


6
Mark G Johnson, Edwin L Hudson: Variable delay line phase-locked loop circuit synchronization system. MIPS Computer Systems, Townsend and Townsend, March 31, 1992: US05101117 (63 worldwide citation)

A system for synchronizing the operation of a CPU and coprocessor operating from a common clock signal includes a first voltage controlled delay line connected to receive the clock signal and delay it by a fixed time interval before supplying it to one of the CPU or coprocessor. A second voltage con ...


7
Marvin A Mills Jr, Lester M Crudele: Write buffer. MIPS Computer Systems, Kenyon & Kenyon, February 14, 1989: US04805098 (63 worldwide citation)

Apparatus is disclosed for buffering writes from a CPU to main memory, in which sequential write requests to the same address are gathered and combined into a single write request. The embodiment described does not permit gathering with the write request in the buffer which is next scheduled for act ...


8
Craig C Hansen: Method and apparatus for precise floating point exceptions. MIPS Computer Systems, Townsend and Townsend, November 7, 1989: US04879676 (49 worldwide citation)

In data processing systems of the type operable to perform floating point computations there is provided a method, and apparatus implementing that method, for predicting, in advance of the floating point computation, whether or not the computation will produce a floating point exception (e.g., overf ...


9
John P Moussouris, Lester M Crudele, Steven A Przybylski: System having an address generating unit and a log comparator packaged as an integrated circuit seperate from cache log memory and cache data memory. MIPS Computer Systems, Kenyon & Kenyon, May 12, 1992: US05113506 (47 worldwide citation)

A cache-based computer architecture is disclosed in which the address generating unit and the tag comparator are packaged together and separately from the cache RAMs. If the architecture supports virtual memory, an address translation unit may be included on the same chip as, and logically between, ...


10
Thomas J Riordan, Paul S Ries, Edwin L Hudson, Earl A Killian: Processor controlled interface with instruction streaming. Mips Computer Systems, Townsend and Townsend, June 25, 1991: US05027270 (46 worldwide citation)

A processor controlled interface between a processor, instruction cache, and main memory provides for simultaneously refilling the cache with an instruction block from main memory and processing the instructions in the block while they are being written to the cache.