1
Thomas Hoffmann, Scott E Thompson: Semiconductor devices having fin structures and fabrication methods thereof. Mie Fujitsu Semiconductor, Baker Botts L, June 9, 2015: US09054219 (8 worldwide citation)

A method of fabricating semiconductor devices includes providing a semiconducting substrate. The method also includes defining a heavily doped region at a surface of the semiconducting substrate in at least one area of the semiconducting substrate, where the heavily doped region includes a heavily d ...


2
Sameer Pradhan, Dalong Zhao, Lingquan Wang, Pushkar Ranade, Lance Scudder: Semiconductor devices with dopant migration suppression and method of fabrication thereof. Mie Fujitsu Semiconductor, Baker Botts L, August 18, 2015: US09112057 (6 worldwide citation)

A method of fabricating a semiconductor device includes providing a substrate having a semiconducting surface and forming a first epitaxial layer on the semiconducting surface. The first epitaxial layer includes a first semiconducting material doped in-situ with at least one dopant of a first conduc ...


3
Dalong Zhao, Pushkar Ranade, Bruce McWilliams: Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same. Mie Fujitsu Semiconductor, Baker Botts L, July 28, 2015: US09093550 (6 worldwide citation)

Semiconductor manufacturing processes include forming conventional channel field effect transistors (FETs) and deeply depleted channel (DDC) FETs on the same substrate and selectively forming a plurality of gate stack types where those different gate stack types are assigned to and formed in connect ...


4
Lawrence T Clark, David A Kidd, Chao Wu Chen: Integrated circuit process and bias monitors and related methods. Mie Fujitsu Semiconductor, Baker Botts L, August 18, 2015: US09112484 (5 worldwide citation)

An integrated circuit device can include at least one oscillator stage having a current mirror circuit comprising first and second mirror transistors of a first conductivity type, and configured to mirror current on two mirror paths, at least one reference transistor of a second conductivity type ha ...


5
Teymur Bakhishev, Sameer Pradhan, Thomas Hoffmann, Sachin R Sonkusale: Method for fabricating a transistor device with a tuned dopant profile. Mie Fujitsu Semiconductor, Baker Botts L, March 29, 2016: US09299801 (3 worldwide citation)

A transistor device with a tuned dopant profile is fabricated by implanting one or more dopant migrating mitigating material such as carbon. The process conditions for the carbon implant are selected to achieve a desired peak location and height of the dopant profile for each dopant implant, such as ...


6
Lawrence T Clark: Bit interleaved low voltage static random access memory (SRAM) and related methods. Mie Fujitsu Semiconductor, Baker Botts L, June 30, 2015: US09070477 (2 worldwide citation)

A method can include applying a device power supply voltage to an integrated circuit including a static random access memory (SRAM) with transistors having at least a first threshold voltage (Vt); applying an array power supply voltage to cells of the SRAM that is near or below Vt; and in a write op ...


7
Lawrence T Clark, Scott E Thompson, Richard S Roy, Robert Rogenmoser, Damodar R Thummalapally: Integrated circuit devices and methods. Mie Fujitsu Semiconductor, Baker Botts L, June 7, 2016: US09362291 (2 worldwide citation)

An integrated circuit can include multiple SRAM cells, each including at least two pull-up transistors, at least two pull-down transistors, and at least two pass-gate transistors, each of the transistors having a gate; at least one of the pull-up transistors, the pull-down transistors, or the pass-g ...


8
Scott E Thompson, Lucian Shifren, Pushkar Ranade, Yujie Liu, Sung Hwan Kim, Lingquan Wang, Dalong Zhao, Teymur Bakhishev, Thomas Hoffmann, Sameer Pradhan, Michael Duane: High uniformity screen and epitaxial layers for CMOS devices. Mie Fujitsu Semiconductor, Baker Botts L, November 24, 2015: US09196727 (2 worldwide citation)

A transistor and method of fabrication thereof includes a screening layer formed at least in part in the semiconductor substrate beneath a channel layer and a gate stack, the gate stack including spacer structures on either side of the gate stack. The transistor includes a shallow lightly doped drai ...


9
Lawrence T Clark, David A Kidd, Augustine Kuo: Integrated circuit device body bias circuits and methods. Mie Fujitsu Semiconductor, Baker Botts L, August 18, 2015: US09112495 (2 worldwide citation)

A system having an integrated circuit (IC) device can include a die formed on a semiconductor substrate and having a plurality of first wells formed therein, the first wells being doped to at least a first conductivity type; a global network configured to supply a first global body bias voltage to t ...


10
Lawrence T Clark, Lucian Shifren, Richard S Roy: Dynamic random access memory (DRAM) with low variation transistor peripheral circuits. Mie Fujitsu Semiconductor, Baker Botts L, August 30, 2016: US09431068 (1 worldwide citation)

A dynamic random access memory (DRAM) can include at least one DRAM cell array, comprising a plurality of DRAM cells, each including a storage capacitor and access transistor; a body bias control circuit configured to generate body bias voltage from a bias supply voltage, the body bias voltage being ...