Timothy L Jackson, Tim E Murphy: Methods of fabrication of semiconductor dice having back side redistribution layer accessed using through-silicon vias and assemblies thereof. MicronTechnology, TraskBritt PC, November 8, 2005: US06962867 (430 worldwide citation)

An apparatus and method of rerouting redistribution lines from an active surface of a semiconductor substrate to a back surface thereof and assembling and packaging individual and multiple semiconductor dice with such rerouted redistribution lines formed thereon. The semiconductor substrate includes ...

Kristy A Campbell: Method of forming a variable resistance memory device comprising tin selenide. MicronTechnology, Dickstein Shapiro, July 6, 2010: US07749853 (8 worldwide citation)

A memory device, such as a PCRAM, including a chalcogenide glass backbone material with germanium telluride glass and methods of forming such a memory device.

Warren M Farnworth, Larry D Kinsman, Walter L Moden: Semiconductor device socket, assembly and methods. MicronTechnology, TraskBritt, August 27, 2002: US06442044 (6 worldwide citation)

A socket that secures bare and minimally packaged semiconductor devices substantially perpendicularly relative to a carrier substrate. The socket includes intermediate conductive elements and a member which moves the intermediate conductive elements between an insertion position and a biased positio ...

Morley J Weyerman: Belt-feed trim and form apparatus. MicronTechnology, Kirkpatrick & Lockhart, February 29, 2000: US06029329 (2 worldwide citation)

An apparatus is provided that increases the efficiency of material handling apparatus, such as those used to trim and form electrical leads on solid state electrical devices. The apparatus includes a plurality of rotatable pulleys, an endless belt capable of retaining devices to be processed that is ...

Chong Chin Hui, David J Corisis, Choon Kuan Lee: Interposer structure with embedded capacitor structure, and methods of making same. MicronTechnology, Perkins Coie, February 18, 2014: US08653625

A device is disclosed which includes an interposer, at least one capacitor formed at least partially within an opening formed in the interposer and an integrated circuit that is operatively coupled to the interposer. A method is disclosed which includes obtaining an interposer having at least one ca ...

Ferdinando Bedeschi: Memory device having address and command selectable capabilities. MicronTechnology, Knobbe Martens Olson & Bear, February 10, 2015: US08954821

Subject matter disclosed herein relates to memory management, and more particularly to partitioning a memory based on memory attributes.

Stephen Tang: Via formation for cross-point memory. MicronTechnology, Knobbe Martens Olson & Bear, April 30, 2013: US08431446

Embodiments disclosed herein may relate to electrically conductive vias in cross-point memory array devices. In an embodiment, the vias may be formed using a lithographic operation also utilized to form electrically conductive lines in a first electrode layer of the cross-point memory array device.

William Frank Witcraft, Hongyue Liu, Joel A Drewes: Magnetic non-volatile memory coil layout architecture and process integration scheme. MicronTechnology, Knobbe Martens Olson & Bear, December 8, 2005: US20050270831-A1

The invention relates to methods and apparatus that allow data to be stored in a magnetic memory cell, such as a giant magneto-resistance (GMR) cell, of a magnetoresistive random access memory (MRAM). Embodiments of the invention advantageously wind a word line around a magnetic memory cell to incre ...

Vo Huy T, Merritt Todd A, Bunker Layne G: An embedded dram architecture with local data drivers and programmable number of data read and data write lines. Microntechnology, October 21, 2002: TW507213

A DRAM architecture configures memory cells into a predetermined number of arrays. Each array has its own row decoders and sense amplifiers. A data path circuit containing local drivers and data read and write lines is associated with each of the arrays in a first direction. The respective connectio ...

Sher Joseph C, Smith Eric J: Method and apparatus for programming anti-fuses using internally generated programming voltage. Microntechnology, March 25, 2000: KR1019980709806

PURPOSE: A method and apparatus for programming anti-fuses with a sufficiently high voltage is provided for a consistently low resistance of the programmed anti-fuse without overstressing other components of the integrated circuit. CONSTITUTION: A programming circuit for an anti-fuse utilizes a boot ...