1
Suresh N Rajan: Methods and apparatus of stacking DRAMs. MetaRAM, Zilka Kotab PC, May 27, 2008: US07379316 (108 worldwide citation)

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


2
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit. MetaRAM, Zilka Kotab PC, June 10, 2008: US07386656 (87 worldwide citation)

A memory circuit power management system and method are provided. An interface circuit is in communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to perform a power management operation in association with only a portion of the memory circuits


3
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: Interface circuit system and method for performing power management operations utilizing power management signals. MetaRAM, Zilka Kotab PC, December 30, 2008: US07472220 (84 worldwide citation)

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for communicating a first number of power management ...


4
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: System and method for power management in memory systems. MetaRAM, Zilka Kotab PC, September 15, 2009: US07590796 (82 worldwide citation)

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of physical memory circuits and a system. The interface circuit is operable to interface the physical memory circuits and the system for simulating at least one virtual ...


5
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: System and method for simulating an aspect of a memory circuit. MetaRAM, Zilka Kotab PC, October 27, 2009: US07609567 (81 worldwide citation)

A system and method are provided for simulating an aspect of a memory circuit. Included is an interface circuit that is in communication with a plurality of memory circuits and a system. Such interface circuit is operable to interface the memory circuits and the system for simulating at least one me ...


6
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits. MetaRAM, Zilka Kotab PC, June 24, 2008: US07392338 (81 worldwide citation)

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for autonomously performing a power management operat ...


7
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: Power saving system and method for use with a plurality of memory circuits. MetaRAM, Zilka Kotab PC, August 25, 2009: US07580312 (80 worldwide citation)

A power saving system and method are provided. In use, at least one of a plurality of memory circuits is identified that is not currently being accessed. In response to the identification of the at least one memory circuit, a power saving operation is initiated in association with the at least one m ...


8
Suresh Natarajan Rajan, Keith R Schakel, Michael John Sebastian Smith, David T Wang, Frederick Daniel Weber: Interface circuit system and method for performing power saving operations during a command-related latency. MetaRAM, Zilka Kotab PC, August 25, 2009: US07581127 (80 worldwide citation)

A memory circuit power management system and method are provided. In use, an interface circuit is in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing a power management operation in associ ...


9
Suresh N Rajan: Methods and apparatus of stacking DRAMs. MetaRAM, Zilka Kotab PC, October 6, 2009: US07599205 (80 worldwide citation)

Large capacity memory systems are constructed using stacked memory integrated circuits or chips. The stacked memory chips are constructed in such a way that eliminates problems such as signal integrity while still meeting current and future memory standards.


10
Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel: Memory circuit system and method. Rajan Suresh Natarajan, Smith Michael John Sebastian, Schakel Keith R, Wang David T, Weber Frederick Daniel, Metaram, KOTAB Dominic M, August 23, 2007: WO/2007/095080 (79 worldwide citation)

A memory circuit system and method are provided. In one embodiment, an interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints ...