1
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, March 7, 2000: US06034882 (945 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for contacts. ...


2
N Johan Knall, Mark Johnson: Three-dimensional memory array and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, July 16, 2002: US06420215 (601 worldwide citation)

A multi-level memory array is described employing rail-stacks. The rail-stacks include a conductor and semiconductor layers. The rail-stacks are generally the diode is located in one rail-stack and the other half in the other rail-stack.


3
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 6, 2001: US06185122 (505 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


4
Andrew J Walker, Mark G Johnson, N Johan Knall, Igor G Kouznetsov, Christopher J Petti: Nonvolatile memory on SOI and compound semiconductor substrates and method of fabrication. Matrix Semiconductor, Pamela J Squyres, May 3, 2005: US06888750 (302 worldwide citation)

A nonvolatile memory array is provided. The array includes an array of nonvolatile memory devices, at least one driver circuit, and a substrate. The at least one driver circuit is not located in a bulk monocrystalline silicon substrate. The at least one driver circuit may be located in a silicon on ...


5
Mark G Johnson, Thomas H Lee, Vivek Subramanian, Paul Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Brinks Hoffer Gilson & Lione, November 19, 2002: US06483736 (294 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


6
Mark G Johnson, Thomas H Lee, Vivek Subramanian, P Michael Farmwald, James M Cleeves: Vertically stacked field programmable nonvolatile memory and method of fabrication. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, February 26, 2002: US06351406 (287 worldwide citation)

A very high density field programmable memory is disclosed. An array is formed vertically above a substrate using several layers, each layer of which includes vertically fabricated memory cells. The cell in an N level array may be formed with N+1 masking steps plus masking steps needed for cont ...


7
Calvin K Li, N Johan Knall, Michael A Vyvoda, James M Cleeves, Vivek Subramanian: Patterning three dimensional structures. Matrix Semiconductor, Blakely Sokoloff Taylor & Zafman, September 30, 2003: US06627530 (283 worldwide citation)

The invention is directed to a method of forming a three dimensional circuit including introducing a three dimensional circuit over a substrate. In one embodiment, the three dimensional circuit includes a circuit structure in a stacked configuration between a first signal line and a second signal li ...


8
Mark G Johnson: Vertically-stacked, field-programmable, nonvolatile memory and method of fabrication. Matrix Semiconductor, Brinks Hofer Gilson & Lione, February 25, 2003: US06525953 (274 worldwide citation)

A three-dimensional, field-programmable, non-volatile memory includes multiple layers of first and second crossing conductors. Pillars are self-aligned at the intersection of adjacent first and second crossing conductors, and each pillar includes at least an anti-fuse layer. The pillars form memory ...


9
Thomas H Lee, Vivek Subramanian, James M Cleeves, Andrew J Walker, Christopher J Petti, Igor G Kouznetzov, Mark G Johnson, Paul Michael Farmwald, Brad Herner: Monolithic three dimensional array of charge storage devices containing a planarized surface. Matrix Semiconductor, Foley & Lardner, April 19, 2005: US06881994 (250 worldwide citation)

There is provided a monolithic three dimensional array of charge storage devices which includes a plurality of device levels, wherein at least one surface between two successive device levels is planarized by chemical mechanical polishing.


10
Andrew J Walker, En Hsing Chen, Sucheta Nallamothu, Roy E Scheuerlein, Alper Ilkbahar, Luca Fasoli, Igor Koutnetsov, Christopher Petti: Method for fabricating programmable memory array structures incorporating series-connected transistor strings. Matrix Semiconductor, Zagorin O Brien Graham, February 28, 2006: US07005350 (246 worldwide citation)

A three-dimensional flash memory array incorporates thin film transistors having a charge storage dielectric arranged in series-connected NAND strings to achieve a 4F2 memory cell layout. The memory array may be programmed and erased using only tunneling currents, and no leakage paths are formed thr ...