1
Fwu Iuan Hshieh: Switching speed improvement in DMO by implanting lightly doped region under gate. Magepower Semiconductor, Bo In Lin, July 30, 2002: US06426260 (123 worldwide citation)

The preset invention discloses an improved method for fabricating a MOSFET transistor on a substrate to improve the device ruggedness. The fabrication method includes the steps of: (a) forming an epi-layer of a first conductivity type as a drain region on the substrate and then growing an gate oxide ...


2
Fwu Iuan Hshieh: Semiconductor cell array with high packing density. MagePower Semiconductor, Kam T Tam, December 21, 1999: US06005271 (88 worldwide citation)

A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) cell array formed on a semiconductor substrate includes a major surface formed with a plurality of MOSFET cells. Each semiconductor cell in the cell array is geometrically configured with a base portion and a plurality of protruding porti ...


3
Fwu Iuan Hshieh, Koon Chong So: Method of forming a semiconductor structure having reduced threshold voltage and high punch-through tolerance. MagePower Semiconductor, Kam T Tam, May 25, 1999: US05907776 (73 worldwide citation)

A power MOSFET (Metal Oxide Semiconductor Field Effect Transistor) device formed on a semiconductor substrate having a body region of a first conductivity type diffused in a semiconductor substrate with an epitaxial layer of a second conductivity type. There is also a source region of a second condu ...


4
Fwu Iuan Hshieh: Double gate-oxide for reducing gate-drain capacitance in trenched DMOS with high-dopant concentration buried-region under trenched gate. MagePOWER Semiconductor, Bo In Lin, July 17, 2001: US06262453 (65 worldwide citation)

This invention discloses a DMOS power device supported on a substrate. The DOS power device includes a drain of a first conductivity type disposed at a bottom surface of the substrate. The DMOS power device further includes a gate disposed in a trench opened from a top surface of the substrate, the ...


5
Fwu Iuan Hshieh: Enhancing DMOS device ruggedness by reducing transistor parasitic resistance and by inducing breakdown near gate runners and termination area. Magepower Semiconductor, Bo In Lin, February 29, 2000: US06031265 (52 worldwide citation)

This invention discloses a vertical DMOS power device formed in a semiconductor substrate with a top surface and a bottom surface. The power device includes a core cell area and a gate runner area. The power device includes a plurality of vertical DMOS transistor cells disposed in the core cell area ...


6
Fwu Iuan Hshieh: Method of forming a semiconductor structure with uniform threshold voltage and punch-through tolerance. MagePower Semiconductor, Kam T Tam, April 18, 2000: US06051468 (46 worldwide citation)

A MOSFET (Metal Oxide Semiconductor Field Effect Transistors) structure is fabricated by first forming a plurality of trenches in a semiconductor substrate which includes a major surface. The trenches are then lined with insulating material and thereafter filled with conductive material. The process ...


7
Fwu Iuan Hshieh: Trenched DMOS device provided with body-dopant redistribution-compensation region for preventing punch through and adjusting threshold voltage. Magepower Semiconductor, Bo In Lin, January 9, 2001: US06172398 (38 worldwide citation)

This invention discloses a vertical DMOS transistor cell formed in a semiconductor substrate of a first conductivity type with a top surface and a bottom surface. The vertical DMOS transistor cell includes a trenched gate comprising polysilicon filling a trench opened from the top surface disposed s ...


8
Fwu Iuan Hshieh, Kong Chong So, Danny Chi Nim: DMOS transistors with diffusion merged body regions manufactured with reduced number of masks and enhanced ruggedness. Magepower Semiconductor Corporation, Bo In Lin, October 26, 1999: US05973361 (23 worldwide citation)

A new transistor cell is disclosed in this invention which is formed in a semiconductor substrate with a drain region of a first conductivity type formed at a bottom surface of the substrate. The DMOS cell includes a polysilicon layer constituting a gate supported on a top surface of the substrate, ...


9
Fwu Iuan Hshieh, Shang Lin Weng, David Haksung Koh, Chanh Ly: MOSFET device to reduce gate-width without increasing JFET resistance. MagePower Semiconductor, Bo In Lin, April 11, 2000: US06049104 (22 worldwide citation)

The present invention discloses a method for fabricating a MOSFET device supported on a substrate. The method includes the steps of (a) growing an oxide layer on the substrate followed by depositing a polysilicon layer and applying a gate mask for performing an undercutting dry etch for patterning a ...


10
Fwu Iuan Hshieh: Cell density improvement in planar DMOS with farther-spaced body regions and novel gates. Magepower Semiconductor Corporation, Bo In Lin, April 13, 1999: US05894150 (18 worldwide citation)

This invention discloses a DMOS planar power device having a plurality of transistor cells formed in a semiconductor substrate with a drain region of a first conductivity type disposed at a bottom surface of the substrate. Each of the DMOS transistor cells includes a polysilicon segment constituting ...