Yao Wen Chang, Wen Jer Tsai, Tao Cheng Lu: Method of controlling multi-state NROM. Macronix International, Jiawei Huang, J C Patents, November 20, 2001: US06320786 (308 worldwide citation)

A method of controlling the multi-state NROM. A program is executed to inject electric charges that are trapped inside a nitride layer of the NROM. The amount of electric charges trapped inside the nitride layer is controlled so that the memory cell can have different threshold voltages. To read fro ...

Hsiang Lan Lung: Self-aligned, programmable phase change memory. Macronix International, Mark A Haynes, Haynes Beffel & Wolfeld, June 17, 2003: US06579760 (300 worldwide citation)

A self-aligned, nonvolatile memory structure based upon phase change materials, including chalcogenides, can be made with a very small area on an integrated circuit. The manufacturing process results in self-aligned memory cells requiring only two array-related masks defining the bit lines and word ...

Fuh Cheng Jong, Kent Kuohua Chang: Method of reading two-bit memories of NROM cell. Macronix International, Powell Goldstein Frazer & Murphy, November 26, 2002: US06487114 (259 worldwide citation)

A method of reading two-bit information in Nitride Read only memory (NROM) cell simultaneously. According to outputted voltage in drain or source of the NROM, it can identify a logical two-bit combination massage of the NROM. The method includes: grounding the source of the NROM; inputting a voltage ...

Hsiang Lan Lung: Spacer chalcogenide memory method and device. Macronix International, Ernest J Beffel Jr, Haynes Beffel & Wolfeld, March 8, 2005: US06864503 (230 worldwide citation)

The present invention includes devices and methods to form memory cell devices including a spacer comprising a programmable resistive material alloy. Particular aspects of the present invention are described in the claims, specification and drawings.

Chin Yi Huang, Huei Huarng Chen, Yun Chang, Samuel C Pan: Method of making nonvolatile memory devices having reduced resistance diffusion regions. Macronix International, Mark A Haynes, Haynes & Beffel, January 23, 2001: US06177317 (219 worldwide citation)

A method is described for manufacturing nonvolatile memory devices having reduced resistance diffusion regions. One embodiment of the method includes forming a multilayer structure over a substrate which includes a tunnel oxide layer, a polysilicon layer, and an etch stop layer. A photoresist maskin ...

Chong Jen Huang, Hsin Huei Chen, Lenvis Liu, Tony Wang, Frank Chiou: Method for manufacturing flash memory device with dual floating gates and two bits per cell. Macronix International, August 7, 2001: US06271090 (214 worldwide citation)

A method for manufacturing a flash memory device with dual floating gates is disclosed. The method use a self-align etching technique to form dual floating gates by using dual spacers as masks. First of all, a semiconductor substrate having a first insulating layer thereon and a first conductive lay ...

Tom D Yiu, Fuchia Shone, Tien Ler Lin, Ray L Wan: Flash EPROM integrated circuit architecture. Macronix International, Haynes & Davis, June 11, 1996: US05526307 (209 worldwide citation)

Contactless flash EPROM cell and array designs, and methods for fabricating the same result in a dense, segmentable flash EPROM chip. The flash EPROM cell is based on a drain-source-drain configuration, in which the single source diffusion is shared by two columns of transistors. The module includes ...

Hsiang Lan Lung: Self-aligned small contact phase-change memory method and device. Macronix International, Ernest J Beffel Jr, Haynes Beffel & Wolfeld, May 22, 2007: US07220983 (201 worldwide citation)

The invention relates to a novel memory cell structure and process to fabricate chalcogenide phase change memory. More particularly, it produces a small cross-sectional area of a chalcogenide-electrode contact part of the phase change memory, which affects the current/power requirement of the chalco ...

Chung Wen Ma, Chun Hung Lin, Tai Yao Lee, Li Jen Lee, Ju Xu Lee, Ting Chung Hu: Method and system for managing a flash memory mass storage system. Macronix International, Mark A Wilson Sonsini Goodrich & Rosati Haynes, September 21, 1999: US05956473 (201 worldwide citation)

The present application discloses methods to provide defect management, wear leveling and data security to a mass storage system implemented using flash memory. The flash memory is organized into a plurality of blocks. Each block has a special region for storing its attributes. In defect management, ...

Jiun Ren Lai, Chien Wei Chen: Pitch reduction in semiconductor fabrication. Macronix International, Stout Uxa Buyan & Mullins, May 11, 2004: US06734107 (200 worldwide citation)

A method for forming transistor devices having a reduced pitch. The pitch of the formed devices can be reduced to, e.g., half that of conventional devices by using current photolithography conditions. Since the pitch of the devices can be reduced, the device integration can be increased, resulting i ...