1
Michael D Rostoker: Multi-chip semiconductor arrangements using flip chip dies. LSI Logic Corporation, Hongiman Miller Schwartz and Cohn, March 21, 1995: US05399898 (331 worldwide citation)

Multi-chip, multi-tier semiconductor arrangements based upon single and double-sided flip-chips are described. The double-sided flip chips provide raised bump contact means on both major surfaces of a die and provided connections to internal signals within the die, feed through connections between c ...


2
Carlos Dangelo, Daniel Watkins, Doron Mintz: Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including interactive system for hierarchical display of control and dataflow information. LSI Logic Corporation, Oppenheimer Wolff & Donnelly, September 1, 1998: US05801958 (264 worldwide citation)

A technique for hierarchical display of control and dataflow graphs allowing a user to view hierarchically filtered control and dataflow information related to a design. The technique employs information inherent in the design description and information derived from design synthesis to identify "mo ...


3
Nicholas F Pasch, Nicholas K Eib, Colin D Yates, Shumay Dou: System and method for performing optical proximity correction on the interface between optical proximity corrected cells. LSI Logic Corporation, Beyer Weaver Thomas, July 23, 2002: US06425117 (260 worldwide citation)

The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distan ...


4
Mario Garza, Nicholas K Eib, John V Jensen, Keith K Chao: Performing optical proximity correction with the aid of design rule checkers. LSI Logic Corporation, Hickman Beyer & Weaver, January 6, 1998: US05705301 (257 worldwide citation)

A method is disclosed for identifying regions of an integrated circuit layout design where optical proximity correction will be most useful and then performing optical proximity correction on those regions only. More specifically, the method includes the following steps: (a) analyzing an integrated ...


5
V Swamy Irrinki, Tuan L Phan, William D Schwarz: Redundancy analysis for embedded memories with built-in self test and built-in self repair. LSI Logic Corporation, Akin Gump Strauss Hauer & Feld, May 23, 2000: US06067262 (250 worldwide citation)

An efficient methodology for detecting and rejecting faulty integrated circuits with embedded memories utilizing stress factors during the manufacturing production testing process. In the disclosed embodiment of the invention, a stress factor is applied to an integrated circuit having built-in-self- ...


6
Nicholas Pasch, Nicholas Eib, Jeffrey Dong: System and method for performing optical proximity correction on macrocell libraries. LSI Logic Corporation, Fenwick & West, October 28, 1997: US05682323 (246 worldwide citation)

The system and method performs optical proximity correction on an integrated circuit (IC) mask design by initially performing optical proximity correction on a library of cells that are used to create the IC. The pre-tested cells are imported onto a mask design. All cells are placed a minimum distan ...


7
Mario Garza, John V Jensen, Nicholas K Eib, Keith K Chao: Optical proximity correction method and apparatus. LSI Logic Corporation, July 31, 2001: US06269472 (244 worldwide citation)

Disclosed is a method for correcting a layout design using a design rule checker. The method includes providing a layout design file having the layout design that is to be corrected for optical proximity by the design rule checker. Providing a run set to the design rule checker. The run set includes ...


8
Thomas F Heil, Martin H Francis, Rodney A DeKoning, Bret S Weber: System and method for peer-to-peer accelerated I/O shipping between host bus adapters in clustered computer network. LSI Logic Corporation, January 9, 2001: US06173374 (239 worldwide citation)

The present invention retrieves data across independent computer nodes of a server cluster by providing for I/O shipping of block level requests to peer intelligent host-bus adapters (hereinafter referred to as HBA). This peer-to-peer distribution of block I/O requests is transparent to the host. Th ...


9
Michael D Rostoker, James S Koford, Ranko Scepanovic, Edwin R Jones, Gobi R Padmanahben, Ashok K Kapoor, Valeriy B Kudryavtsev, Alexander E Andreev, Stanislav V Aleshin, Alexander S Podkolzin: Hexagonal field programmable gate array architecture. LSI Logic Corporation, Mitchell Silberberg & Knupp, July 7, 1998: US05777360 (226 worldwide citation)

Several inventions are disclosed. A cell architecture using hexagonal shaped cells is disclose. The architecture is not limited to hexagonal shaped cells. Cells may be defined by clusters of two or more hexagons by triangles, by parallelograms, and by other polygons enabling a variety of cell shapes ...


10
Rodney A DeKoning: Methods and structure for RAID level migration within a logical unit. LSI Logic Corporation, August 14, 2001: US06275898 (224 worldwide citation)

Methods and structures for defining partitions within a RAID storage system LUN such that each partition is managed in accordance with RAID management techniques independent of the other partitions. The total data storage of the LUN is subdivided and mapped into a plurality of partitions also referr ...



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