1
Steven J Frank, Henry Burkhardt III, Linda O Lee, Nathan Goodman, Benson I Margulies, Frederick D Weber: Multiprocessor digital data processing system. Kendall Square Research Corporation, Lahive & Cockfield, October 8, 1991: US05055999 (96 worldwide citation)

A multiprocessor digital data processing system comprises a plurality of processing cells arranged in a hierarchy of rings. The system selectively allocates storage and moves exclusive data copies from cell to cell in response to access requests generated by the cells. Routing elements are employed ...


2
Steven J Frank, Henry Burkhardt III, James B Rothnie, David I Epstein, Stephen W Morss, Dana R Kelly, Paul A Binder: Dynamic packet routing network. Kendall Square Research Corporation, Lahive & Cockfield, January 25, 1994: US05282201 (78 worldwide citation)

A digital data communications apparatus includes first and second processing groups, each made up of a plurality of processing cells interconnected by an associated bus. An element (RRC) transfers information packets generated by the processing cells between the first and second processing groups. T ...


3
Steven J Frank, Henry Burkhardt III, James B Rothnie, William F Mann: High-speed packet switching apparatus and method. Kendall Square Research Corporation, Lahive & Cockfield, August 2, 1994: US05335325 (75 worldwide citation)

An improved digital packet switching apparatus enabling enhanced packet transmission and high bandwidth packet transfer. The digital packet switching methods and apparatus permit selectively switching digital signal packet between a set of nodes. The invention includes multiple processing cells, eac ...


4
Steven J Frank, Henry Burkhardt III, Linda Q Lee, Nathan Goodman, Benson I Margulies, Frederick D Weber: Shared memory multiprocessor system and method of operation thereof. Kendall Square Research Corporation, Lahive & Cockfield, March 22, 1994: US05297265 (74 worldwide citation)

A digital data processing apparatus has plural processing cells, each with a memory element that stores data page made up of plural subpages. At least one of the cells includes a CPU that can request access to a data subpage. A memory manager responds to selected data access requests by (i) allocati ...


5
Steven J Frank, Henry Burkhardt III, James B Rothnie, Benson I Margulies, Frederick D Weber, Linda Q Lee, Glen Dudek, William F Mann, Edward N Kittlitz, Ruth Shelley: Shared memory multiprocessor with data hiding and post-store. Kendall Square Research Corporation, Lahive & Cockfield, October 5, 1993: US05251308 (65 worldwide citation)

A digital data processing system includes a plurality of central processor units which share and access a common memory through a memory management element. The memory management element permits, inter alia, data in the common memory to be accessed in at least two modes. In the first mode, all centr ...


6
Steven J Frank, Paul A Binder: Dynamic hierarchial associative memory. Kendall Square Research Corporation, Lahive & Cockfield, August 23, 1994: US05341483 (62 worldwide citation)

An associative memory having an associativity of 2.sup.q, where (q) is an integer greater than or equal to one, is provided for storing information relating to data. The memory includes (n) tables, each having a plurality of entries for storing signals associated with data descriptors having a commo ...


7
Mark A Kaufman, Fernando Oliveira: Digital data processor with improved checkpointing and forking. Kendall Square Research Corporation, Lahive & Cockfield, May 17, 1994: US05313647 (58 worldwide citation)

A digital data processing apparatus includes a processing element that executes a process for generating requests for access to mapped data in a memory element. The apparatus also includes a fork/checkpoint-signalling element that generates "new-process signals" which delineate new time intervals. T ...


8
Steven J Frank, Henry Burkhardt III, Frederick D Weber: Register bus multiprocessor system with shift. Kendall Square Research Corporation, Lahive & Cockfield, June 2, 1992: US05119481 (48 worldwide citation)

A digital data processing apparatus includes a shift-register bus that transfers packets of digital information. The bus has a plurality of digital storage and transfer stages connected in series in a ring configuration. A plurality of processing cells, each including at least a memory element, are ...


9
Steven J Frank, Henry Burkhardt III, James B Rothnie, David I Epstein, Stephen W Morss, Dana R Kelly, Paul A Binder: Packet routing switch. Kendall Square Research Corporation, Lahive & Cockfield, July 6, 1993: US05226039 (45 worldwide citation)

A switch is provided for selectively routing digital information packets received from at least first and second external sources to at least first and second external destinations. At least one of the first sources generates an information packet including a datum, or a request therefore, and a cor ...


10
Richard E Leitermann, Neal H Marshall, John C Costello, Gianfranco D Zaccai: Computer system module assembly. Kendall Square Research Corporation, Lahive & Cockfield, June 19, 1990: US04934764 (19 worldwide citation)

A computer system module assembly has modular equipment enclosures slidable and securable in a modular exoskeletal frame structure on a base. The frame structure includes horizontal frame members on which the enclosures slide with pawls movable on a threaded rod to engage studs on the enclosures to ...