1
G Glenn Henry, Rodney E Hooker: Virtual set cache that redirects store data to correct virtual set to avoid virtual set store miss penalty. IP First L L C, E Alan Davis, James W Huffman, September 16, 2003: US06622211 (22 worldwide citation)

A virtual set cache that avoids virtual set store miss penalty. During a query pass of a store operation, only the untranslated physical address bits of the store address are used to index the cache array. In one embodiment, the untranslated physical address bits select four virtual sets of cache li ...


2
G Glenn Henry, Terry Parks: Method and apparatus for performing branch prediction combining static and dynamic branch predictors. IP First L L C, E Alan Davis, James W Huffman, June 12, 2001: US06247122 (21 worldwide citation)

An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A static branch predictor makes a prediction of the outcome of a conditional branch instruction based on the branch test type and the branch target ad ...


3
G Glenn Henry, Terry Parks: Apparatus and method for fast forward branch. IP First L L C, Richard K Huffman, James W Huffman, May 15, 2001: US06233676 (20 worldwide citation)

An apparatus and method are provided for executing a forward branch in a microprocessor. The apparatus has translation logic and instruction fetch logic. The translation logic utilizes a branch predictor to determine if a conditional branch should be taken or not. If the branch is predicted taken, t ...


4
Gerard M Col, G Glenn Henry, Dinesh K Jain: Apparatus and method for speculatively updating global history and restoring same on branch misprediction detection. IP First L L C, E Alan Davis, James W Huffman, February 13, 2001: US06189091 (20 worldwide citation)

An apparatus and method for improving microprocessor performance by improving the prediction accuracy of conditional branch instructions is provided. A dynamic branch predictor speculatively updates global branch history information based on the prediction of a first branch instruction so that the p ...


5
Gerard M Col, G Glenn Henry, Arturo Martin de Nicolas: System for combining adjacent push/pop stack program instructions into single double push/pop stack microinstuction for execution. IP First L L C, Richard K Huffman, James W Huffman, February 19, 2002: US06349383 (15 worldwide citation)

An apparatus and method are provided for combining multiple instructions prescribing accesses to a microprocessor stack into a single micro instruction. The apparatus includes a translator and access alignment logic. The translator receives a first stack access instruction and a second stack access ...


6
Darius D Gaskins, G Glenn Henry: Microprocessor having fuse control and selection of clock multiplier. IP First L L C, Richard K Huffman, James W Huffman, December 12, 2000: US06161188 (10 worldwide citation)

A microprocessor is provided having selective control features to determine its core-to-bus clock ratio. The microprocessor includes a fuse and buffer/control logic. The fuse, fabricated on the microprocessor's metalization or poly layer, can be blown with a laser during fabrication. When blown, the ...


7
G Glenn Henry, Terry Parks: Apparatus and method for executing a single-cycle exchange instruction to exchange contents of two locations in a register file. IP First L L C, Richard K Huffman, James W Huffman, November 7, 2000: US06145075 (9 worldwide citation)

An apparatus and method for exchanging operands within a microprocessor is provided. The apparatus contains a translator for generating a micro instruction that loads a first operand into a second location, and a second operand into a first location without specifying intermediate storage of either ...


8
Gerard M Col: Speculative generation at address generation stage of previous instruction result stored in forward cache for use by succeeding address dependent instruction. IP First L L C, Richard K Huffman, James W Huffman, September 30, 2003: US06629234 (9 worldwide citation)

An apparatus is presented for expediting the execution of address-dependent micro instructions in a pipeline microprocessor. The apparatus computes a speculative result associated with an arithmetic operation, where the arithmetic operation is prescribed by a preceding micro instruction that is yet ...


9
James R Lundberg: Slew-controlled split-voltage output driver. IP First L L C, Richard K Huffman, James W Huffman, July 16, 2002: US06420924 (9 worldwide citation)

A CMOS slew-controlled split-voltage output driver is provided whose I/O logic is supplied at one (higher) voltage level and whose computational logic is supplied at a second (lower) voltage level. The slew-controlled split-voltage output driver includes an output driver circuit, a driver control ci ...


10
Timothy A Elliott, G Glenn Henry: Apparatus and method for fast square root calculation within a microprocessor. IP First L L C, Richard K Huffman, James W Huffman, January 16, 2001: US06175907 (8 worldwide citation)

An apparatus and method for calculating a square root of an operand in a microprocessor are provided. The microprocessor has a plurality of square root instructions, each of which specifies a square root calculation precision. The apparatus includes translation logic and execution logic. The transla ...