1
Ralph E Jennings Jr, Benjamin P Haley Jr, R D Holland, Deborah K Cecil, Anthony E Tassone: Method and apparatus for enabling control of task execution. Intergraph Corporation, Townsend and Townsend and Crew, July 30, 1996: US05542088 (160 worldwide citation)

A system is disclosed which enables a user of a computer system to have direct control over the priorities assigned to the execution of tasks requested by the user. The user establishes a user tolerance level indicative of the delay the user is willing to tolerate before a task is assigned to backgr ...


2
Jeffrey E Bains, Willard W Case: Distributed license administration system using a local policy server to communicate with a license server and control execution of computer programs. Intergraph Corporation, Bromberg & Sunstein, November 26, 1996: US05579222 (157 worldwide citation)

An improved system for administration of license terms for a software product on the network, having an arrangement, for tracking software product usage, with one of the computers acting as a license server. This arrangement permits the license server (i) to identify the current set of nodes that ar ...


3
Howard G Sachs, James Y Cho: Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency. Intergraph Corporation, Townsend and Townsend, February 25, 1992: US05091846 (128 worldwide citation)

A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation ...


4
Howard G Sachs, Siamak Arya: Software scheduled superscalar computer architecture. Intergraph Corporation, Townsend and Townsend and Crew, September 24, 1996: US05560028 (116 worldwide citation)

A computing system is described in which groups of individual instructions are executable in parallel by processing pipelines, and instructions to be executed in parallel by different pipelines are supplied to the pipelines simultaneously. During compilation of the instructions those which can be ex ...


5
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Apparatus for maintaining consistency of a cache memory with a primary memory. Intergraph Corporation, Townsend and Townsend, June 12, 1990: US04933835 (95 worldwide citation)

A microprocessor system is disclosed having a high speed system bus for coupling system elements, and having a dual bus microprocessor with separate ultra-high speed instruction and data cache-MMU interfaces coupled to independently operable instruction and data cache-MMU, respectively. A main memor ...


6
Douglas B Gerull, David M Glenn: System for dynamic segmentation analysis using conversion of relational data into object-oriented data. Intergraph Corporation, Bromberg & Sunstein, June 20, 1995: US05426780 (83 worldwide citation)

Dynamic segmentation of Geographical Information System (GIS) map data, stored in a relational database, converts linear-feature fixed-length attribute arrays, stored as columns in a relational table, into variable length attribute and location arrays for inclusion into an object-oriented map databa ...


7
Howard G Sachs, James Y Cho, Walter H Hollingsworth: Quadword boundary cache system. Intergraph Corporation, Townsend and Townsend, August 22, 1989: US04860192 (82 worldwide citation)

In a cache memory system, multiple-word boundary registers, multiple-word line registers, and a multiple-word boundary detector system provide accelerated access of data contained within the cache memory within the multiple-word boundaries, and provides for effective prefetch of sequentially ascendi ...


8
Howard G Sachs, James Y Cho: Memory address translation system having modifiable and non-modifiable translation mechanisms. Intergraph Corporation, Townsend and Townsend Khourie and Crew, October 19, 1993: US05255384 (75 worldwide citation)

A Cache-Memory Management System provides high speed virtual to real address translation. Address translation logic, comprised of mutually exclusive modifiable and nonmodifiable translation logic, selectively provides real address output responsive to the externally supplied virtual address from the ...


9
Robert J Proebsting: High speed redundant rows and columns for semiconductor memories. Intergraph Corporation, Townsend and Townsend Khourie and Crew, December 28, 1993: US05274593 (73 worldwide citation)

A semiconductor memory having a redundant column is described in which access time is not reduced when the redundant column is employed to replace a defective column. The memory includes a number of columns of memory cells, each column having a corresponding input/output node. A set of input/output ...


10
Jean Louis Ardoin, Richard M Eade, Robert Patience, Alain Falasse, Dave L Brann, Gerard J Attilio, Alfredo Arce: Object relationship management system. Intergraph Corporation, Townsend and Townsend and Crew, September 18, 2001: US06292804 (66 worldwide citation)

A method for maintaining relationships between entities in a computer system, each entity having a plurality nodes, includes the steps of: modifying one of the plurality of nodes; searching for a plurality of dependent nodes from the plurality of nodes coupled to the one node; ordering the plurality ...