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Thomas A Dye, Manuel J Alvarez II, Peter Geiger: PARALLEL COMPRESSION/DECOMPRESSION SYSTEM AND METHOD FOR IMPLEMENTATION OF IN-MEMORY COMPRESSED CACHE IMPROVING STORAGE DENSITY AND ACCESS SPEED FOR INDUSTRY STANDARD MEMORY SUBSYSTEMS AND IN-LINE MEMORY MODULES. Interactive Silicon, Jeffrey C Hood, February 18, 2003: US06523102 (294 worldwide citation)

An ASIC device embedded into the memory subsystem of a computing device used to accelerate the transfer of active memory pages for usage by the system CPU from either compressed memory cache buffer or the addition of a compressed disk subsystem for improved system cost and performance. The Compressi ...


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Thomas A Dye: System and method for managing system memory and/or non-volatile memory using a memory controller with integrated compression and decompression capabilities. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon PC, January 2, 2001: US06170047 (234 worldwide citation)

An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high-speed system peripheral bus such as the PCI bus and couples to system memory. T ...


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Thomas A Dye: Parallel decompression and compression system and method for improving storage density and access speed for non-volatile memory and embedded memory devices. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon PC, November 7, 2000: US06145069 (222 worldwide citation)

A flash memory controller and/or embedded memory controller including MemoryF/X Technology that uses data compression and decompression for improved system cost and performance. The Compression Enhanced Flash Memory Controller (CEFMC) of the present invention preferably uses parallel lossless compre ...


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Thomas A Dye: Memory controller including compression/decompression capabilities for improved data access. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon PC, April 9, 2002: US06370631 (204 worldwide citation)

An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. T ...


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Thomas A Dye: Memory controller including embedded data compression and decompression engines. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon PC, January 9, 2001: US06173381 (198 worldwide citation)

An integrated memory controller (IMC) which includes data compression and decompression engines for improved performance. The memory controller (IMC) of the present invention preferably sits on the main CPU bus or a high speed system peripheral bus such as the PCI bus and couples to system memory. T ...


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Thomas Anthony Dye: Integrated video and memory controller with data processing and graphical processing capabilities. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon, December 14, 1999: US06002411 (152 worldwide citation)

An integrated memory controller (IMC) which incorporates novel memory, graphics, and audio processing capabilities in a single logical unit. The IMC includes numerous significant advances which provide greatly increased performance over prior art systems. The integrated memory controller (IMC) inclu ...


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Thomas A Dye, Manuel J Alvarez II, Peter Geiger: System and method for performing scalable embedded parallel data compression. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon PC, March 27, 2001: US06208273 (136 worldwide citation)

A system and method for performing parallel data compression which processes stream data at more than a single byte or symbol (character) at one time. The parallel compression engine modifies a single stream dictionary based (or history table based) data compression method, such as that described by ...


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Thomas A Dye: System and method for simultaneously displaying a plurality of video data objects having a different bit per pixel formats. Interactive Silicon, Jeffrey C Conley Rose & Tayon Hood, August 22, 2000: US06108014 (73 worldwide citation)

A computer system and graphics controller which stores video data in memory corresponding to a plurality of video objects and presents the video objects on a video monitor, wherein a plurality of the video objects have differing numbers of bits per pixel formats. System memory stores video data in a ...


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Thomas A Dye, Peter D Geiger, Manuel J Alvarez II: Graphics system and method for rendering independent 2D and 3D objects using pointer based display list video refresh operations. Interactive Silicon, Jeffrey C Hood, February 11, 2003: US06518965 (66 worldwide citation)

A spanning based method for rendering and display of 3D graphical data on a display device. The method first parses the geometry data, generates independent vertex-sorted geometric primitives (e.g., triangles) and then performs setup on the geometric primitives. The method then computes horizontal s ...


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Thomas A Dye: Video/graphics controller which performs pointer-based display list video refresh operation. Interactive Silicon, Jeffrey C Hood, Conley Rose & Tayon P C, May 23, 2000: US06067098 (54 worldwide citation)

A graphics controller (IMC) which performs pointer-based and/or display list-based video refresh operations that enable screen refresh data to be assembled on a per window or per object basis, thereby greatly increasing the performance of the graphical display. The graphics controller maintains poin ...