1
William B Buzbee: Use of dynamic translation to collect and exploit run-time information in an optimizing compilation system. Institute for the Development of Emerging Architectures L L C, September 29, 1998: US05815720 (91 worldwide citation)

Dynamic translation is used to produce profile information used to optimize object code for an application. In order to produce optimized object code for the application, source code for the application is compiled to produce first object code for the application. The first object code is used in th ...


2
Jerome C Huck, Peter Markstein, Glenn T Colon Bonet, Alan H Karp, Roger Golliver, Michael Morrison, Gautam B Doshi, Guillermo Juan Rozas: Methods and apparatus for efficient control of floating-point status register. Institute For The Development of Emerging Architectures L L C, November 21, 2000: US06151669 (65 worldwide citation)

A floating-point unit of a computer includes a floating-point computation it, floating-point registers and a floating-point status register. The floating-point status register may include a main status field and one or more alternate status fields. Each of the status fields contains flag and control ...


3
William R Bryg, Stephen G Burger, Gary N Hammond, James O Hays, Jerome C Huck, Jonathan K Ross, Sunil Saxena, Koichi Yamada: Method and apparatus for calculating a page table index from a virtual address. Institute for the Development of Emerging Architectures L L C, David A Plettue, May 21, 2002: US06393544 (60 worldwide citation)

A method and apparatus calculate a page table index from a virtual address. Employs a combined hash algorithm that supports two different hash page table configurations. A “short format” page table is provided for each virtual region, is linear, has a linear entry for each translation in the region, ...


4
James M Hull, Kent Fielden, Hans Mulden, Harshvardhan Sharangpani: Processor utilizing a template field for encoding instruction sequences in a wide-word format. Institute For The Development Of Emerging Architectures L L C, Blakely Sokoloff Taylor & Zafman, July 13, 1999: US05922065 (49 worldwide citation)

A processor having a large register file utilizes a template field for ening a set of most useful instruction sequences in a long instruction word format. The instruction set of the processor includes instructions which are one of the plurality of different instruction types. The execution units of ...


5
Dean Mulla, Sorin Iacobovici: Cache arrangement including coalescing buffer queue for non-cacheable data. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, September 2, 1997: US05664148 (48 worldwide citation)

An apparatus including a cache subsystem arrangement for efficient management of input/output operations and of memory shared by processors in a multiprocessor system. The apparatus includes a central processing unit, an input/output device such as a network device or a display device for example, a ...


6
Dean Mulla, Sorin Iacobovici: Method and apparatus for handling snoops in multiprocessor caches having internal buffer queues. Institute for the Development of Emerging Architectures L L C, Jack A Lenell, July 29, 1997: US05652859 (47 worldwide citation)

A method and apparatus for snooping both cache memory and associated buffer queues in a cache subsystem arrangement. Since there are usually several requests for cache data being handled at any given time under high performance operation of multiple processors, a cache arrangement includes at least ...


7
Tse Yu Yeh, Mircea Poplingher, Kent G Fielden, Hans Mulder, Rajiv Gupta, Dale Morris, Michael Schlansker: Instruction prefetch mechanism utilizing a branch predict instruction. Institute for the Development of Emerging Architectures L L C, Blakely Sokoloff Taylor & Zafman, April 21, 1998: US05742804 (45 worldwide citation)

A processor and method that reduces instruction fetch penalty in the execution of a program sequence of instructions comprises a branch predict instruction that is inserted into the program at a location which precedes the branch. The branch predict instruction has an opcode that specifies a branch ...


8
William R Bryg, Stephen G Burger, Gary N Hammond, Michael L Ziegler: Apparatus and method for a load bias--load with intent to semaphore. Institute for the Development of Emerging Architectures L L C, October 3, 2000: US06128706 (41 worldwide citation)

Apparatus and method for efficiently sharing data in support of hardware he coherency and coordinated in software with semaphore instructions. Accordingly, a new instruction called "Load-Bias" which, in addition to normal load operations, requests a private copy of the data, and hints to the hardwar ...


9
Rory McInerney, Eric Sindelar, Tse Yu Yeh: Processor with apparatus for tracking prefetch and demand fetch instructions serviced by cache memory. Institute for the Development of Emerging Architectures L L C, Blakely Sokoloff Taylor & Zafman, April 3, 2001: US06212603 (33 worldwide citation)

A processor prefetches instructions in a pipelined manner from a first (L1) cache to a local instruction cache, with an instruction pointer device being utilized to select one of a plurality of incoming addresses for fetching purposes. Instructions returned from the L1 cache are stored in an instruc ...


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Gautam B Doshi, Peter Markstein, Alan H Karp, Jerome C Huck, Glenn T Colon Bonet, Michael Morrison: System and method for deferring exceptions generated during speculative execution. Institute for the Development of Emerging Architectures L L C, October 9, 2001: US06301705 (32 worldwide citation)

The present invention is generally directed to a system and method for supporting speculative execution of an instruction set for a central processing unit (CPU) including non-speculative and speculative instructions. In accordance with one aspect of the invention a method includes the steps of eval ...