1
Sargent S Eaton Jr, David R Wooten: Redundancy scheme for a dynamic RAM. Inmos Corporation, Edward D Manzo, June 21, 1983: US04389715 (84 worldwide citation)

A redundancy scheme is described for replacing defective main memory cells in a dynamic RAM with spare memory cells. The spare cells are arranged in groups of spare rows and spare columns of memory cells such that a plurality of groups of spare rows and columns of cells are substituted for defective ...


2
E Henry Stevens, Paul J McClure, Christopher W Hill: Semiconductor contact silicide/nitride process with control for silicide thickness. INMOS Corporation, Edward D Manzo, November 15, 1988: US04784973 (82 worldwide citation)

A titanium silicide/titanium nitride process is disclosed wherein the thickness of the titanium nitride can be regulated with respect to the titanium silicide. In particular, a control layer is formed in the contact opening during a reactive cycle to form a relatively thin (20 to 50 angstrom) contro ...


3
Rahul Sud, Kim C Hardee, John D Heightley: Asynchronously equillibrated and pre-charged static ram. INMOS Corporation, Cook Wetzel & Egan, October 19, 1982: US04355377 (70 worldwide citation)

A static RAM (random access memory) is described wherein fully asynchronous active equilibration and precharging of the RAM's bit lines provides improved memory access time and lower active power dissipation. In the preferred embodiment, each change in the memory's row address is sensed for developi ...


4
Rahul Sud, Kim C Hardee: Redundancy system for high speed, wide-word semiconductor memories. Inmos Corporation, Cook Wetzel & Egan, July 10, 1984: US04459685 (66 worldwide citation)

A redundancy system is described for a high speed, wide-word semiconductor memory having first and second arrays of regular memory cells. The system includes a plurality of spare columns of cells, half of which are located adjacent the first array and half of which are located adjacent the second ar ...


5
Sargent S Eaton Jr, David R Wooten: High speed data transfer for a semiconductor memory. Inmos Corporation, Donald E Egan, James M Wetzel, August 10, 1982: US04344156 (65 worldwide citation)

A system is described for use in a semiconductor memory for rapidly transferring data between a plurality of successive memory locations and a data output buss. The system includes a plurality of data latches for storing data derived from successive locations in memory, and a corresponding plurality ...


6
Rahul Sud, Kim C Hardee, John O Heightley: Redundancy scheme for an MOS memory. INMOS Corporation, John H Moore, August 24, 1982: US04346459 (46 worldwide citation)

A redundancy scheme is described for use with an MOS memory having a main array of memory cells, and a plurality of spare memory cells. Typically, each memory cell is tested for operability by a conventional probe test. When a defective memory cell is found, an on-chip address controller responds to ...


7
James D Allan: CMOS substrate bias generator having only P channel transistors in the charge pump. Inmos Corporation, Edward D Manzo, Roger R Wise, April 8, 1986: US04581546 (41 worldwide citation)

A CMOS substrate bias generator including a PMOS charge pump and a regulator for controlling the operation of the substrate bias generator. The substrate bias generator further includes an input circuit, a reference circuit to provide a reference voltage, a comparison circuit to compare voltage leve ...


8
Paul J McClure, Robert E Jones Jr: Metallic fuse with optically absorptive layer. INMOS Corporation, Edward D Manzo, May 2, 1989: US04826785 (41 worldwide citation)

A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a ...


9
Paul J McClure, Robert E Jones Jr: Metallic fuse with optically absorptive layer. Inmos Corporation, Edward D Manzo, June 19, 1990: US04935801 (38 worldwide citation)

A metallic interconnect includes a fuse portion that is readily vaporized upon exposure to the radiant energy of a laser. A layer of optically absorptive material is formed on top of an aluminum based metallic interconnect and together they are formed by a photolithographic and etch technique into a ...


10
S Sheffield Eaton Jr, Cheng Cheng Hu: Thick oxide field-shield CMOS process. Inmos Corporation, Edward D Manzo, February 18, 1986: US04570331 (37 worldwide citation)

An improved semiconductor structure and the method for fabricating such is disclosed. The invention relates to the use of thick-oxide for improved field-shield isolation especially as applied to dynamic RAMS's and also to its integration into an improved CMOS process. The improved structure has incr ...